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CS5530 数据表(PDF) 32 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5530
功能描述  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5530 数据表(HTML) 32 Page - National Semiconductor (TI)

Back Button CS5530 Datasheet HTML 28Page - National Semiconductor (TI) CS5530 Datasheet HTML 29Page - National Semiconductor (TI) CS5530 Datasheet HTML 30Page - National Semiconductor (TI) CS5530 Datasheet HTML 31Page - National Semiconductor (TI) CS5530 Datasheet HTML 32Page - National Semiconductor (TI) CS5530 Datasheet HTML 33Page - National Semiconductor (TI) CS5530 Datasheet HTML 34Page - National Semiconductor (TI) CS5530 Datasheet HTML 35Page - National Semiconductor (TI) CS5530 Datasheet HTML 36Page - National Semiconductor (TI) Next Button
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32
Revision 4.1
Signal Definitions (Continued)
2.2.8
USB Interface
Signal Name
Pin
No.
Type
Description
POWER_EN
V4
O
Power Enable
This pin enables the power to a self-powered USB hub.
OVER_CUR#
W3
I
5VT
Over Current
This pin indicates the USB hub has detected an overcurrent on the USB.
D+_PORT1
Y2
I/O
USB Port 1 Data Positive
This pin is the Universal Serial Bus Data Positive for port 1.
D–_PORT1
Y1
I/O
USB Port 1 Data Minus
This pin is the Universal Serial Bus Data Minus for port 1.
D+_PORT2
AA2
I/O
USB Port 2 Data Positive
This pin is the Universal Serial Bus Data Positive for port 2.
D–_PORT2
AA1
I/O
USB Port 2 Data Minus
This pin is the Universal Serial Bus Data Minus for port 2.
2.2.9
Game Port and General Purpose I/O Interface
Signal Name
Pin
No.
Type
Description
GPORT_CS#
AD21
O
Game Port Chip Select
GPORT_CS# is asserted upon any I/O reads or I/O writes to I/O Port
200h and 201h.
GPCS#
AF26
O
General Purpose Chip Select
GPCS# is asserted upon any I/O access that matches the I/O address in
the General Purpose Chip Select Base Address Register (F0 Index 70h)
and the conditions set in the General Purpose Chip Select Control Regis-
ter (F0 Index 72h).
GPIO7/SA23
AF23
I/O
5VT
Limited ISA Mode: General Purpose I/Os 7 through 4 or
System Address Bus Lines 23 through 20
These pins can function either as general purpose I/Os or as the upper
four bits of the SA bus. Selection is done through F0 Index 43h[6,2].
Refer to GPIO[3:2] signal description for GPIO function description.
GPIO6/SA22
AE23
GPIO5/SA21
AC21
GPIO4/SA20
AD22
ISA Master Mode: System Address Bus Lines 23 through 20
These pins function as the four MSB (most significant bits) of the SA bus.
GPIO3
AF24
I/O
5VT
General Purpose I/Os 3 and 2
GPIOs can be programmed to operate as inputs or outputs via F0 Index
90h. As an input, the GPIO can be configured to generate an external
SMI. Additional configuration can select if the SMI# is generated on the
rising or falling edge. GPIO external SMI generation/edge selection is
done in F0 Index 92h and 97h.
GPIO2
AF25
I/O
5VT



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