CS5530 datasheet(56/241 Pages) NSC

56 / 241 page

www.national.com

Revision 4.1

Functional Description (Continued)

Configuring Suspend Modulation

Control of the Suspend Modulation feature is accom-

plished using the Suspend Modulation OFF Count Regis-

ter, the Suspend Modulation ON Count Register, and the

Suspend Configuration Register (F0 Index 94h, 95h, and

96h, respectively).

The Power Management Enable Register 1 (F0 Index

80h) contains the global power management enable bit

(bit 0), as well as the enables for the individual activity

speedup timers. The global power management bit must

be enabled for Suspend Modulation and all other power

management resources to function.

Bit 0 of the Suspend Configuration Register (F0 Index

96h) enables the Suspend Modulation feature. Bit 1 con-

trols how SMI events affect the Suspend Modulation fea-

ture. In general this bit should be set to a 1, which causes

SMIs to disable Suspend Modulation until it is re-enabled

by the SMI handler.

The Suspend Modulation OFF and ON Count Registers

(F0 Index 94h and 95h) control two 8-bit counters that rep-

resent the number of 32 µs intervals that the SUSP# pin is

asserted and then deasserted to the processor. These

counters define a ratio which is the effective frequency of

operation of the system while Suspend Modulation is

enabled.

The IRQ and Video Speedup Timer Count registers (F0

Index 8Ch and 8Dh) configure the amount of time which

Suspend Modulation is disabled when the respective

events occur.

SMI Speedup Disable

If the Suspend Modulation feature is being used for CPU

power management, the occurrence of an SMI disables

the Suspend Modulation function so that the system oper-

ates at full speed while in SMM. There are two methods

used to invoke this via bit 1 of the Suspend Configuration

If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer

(F0 Index 8Ch) to temporarily disable Suspend

Modulation when an SMI occurs.

If F0 Index 96h[1] = 1: Disable Suspend Modulation

when an SMI occurs until a read to the SMI Speedup

Disable Register (F1BAR+Memory Offset 08h).

The SMI Speedup Disable Register prevents VSA tech-

nology software from entering Suspend Modulation while

operating in SMM. The data read from this register can be

ignored. If the Suspend Modulation feature is disabled,

reading this I/O location has no effect.

Table 3-13 shows the bit formats of the Suspend Modula-

tion related registers.

Feff =FGX86 x

On Count

On Count + Off Count

Table 3-13. Suspend Modulation Related Registers

Bit

Description

F1BAR+Memory Offset 08h-09h

SMI Speedup Disable Register (Read to Enable)

Reset Value = 0000h

15:0

SMI Speedup Disable: If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register

invokes the SMI handler to re-enable Suspend Modulation.

The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this location has

no effect.

F0 Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GXLV pro-

cessor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when system is power man-

aged using CPU Suspend Modulation. 0 = Disable; 1 = Enable.

The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an

external VGA access (3Bx, 3, 3Dx and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-stan-

dard, but it does allow the power management routines to support an external VGA chip.

IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand-

shake) for a configurable duration when system is power managed using CPU Suspend Modulation:

0 = Disable; 1 = Enable.

The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

Power Management: Global power management: 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for power management resources to function.

CS5530 数据表(PDF) 56 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 56 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载