CS5530 datasheet(58/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.4.2.2

3 Volt Suspend

The CS5530 supports the stopping of the CPU and sys-

tem clocks for a 3 Volt Suspend state. If appropriately con-

figured, via the Clock Stop Control Register (F0 Index

BCh), the CS5530 asserts the SUSP_3V pin after it has

gone through the SUSP#/SUSPA# handshake. The

SUSP_3V pin is a state indicator, indicating that the sys-

tem is in a low-activity state and Suspend Modulation is

active. Thisindicator canbeusedtoput the systeminto a

low-power state (the system clock can be turned off).

The SUSP_3V pin is intended to be connected to the out-

put enable of a clock generator or buffer chip, so that the

clocks to the CPU and the CS5530 (and most other sys-

tem devices) will be stopped. The CS5530 continues to

decrement all of its device timers and respond to external

SMI interrupts after the input clock has been stopped, as

long as the 32 KHz clock continues to oscillate. Any SMI

event or unmasked interrupt pin causes the CS5530 to

deassert the SUSP_3V pin, restarting the system clocks.

As the CPU or other device might include a PLL, the

CS5530 holds SUSP# active for a pre-programmed

period of delay (the PLL re-sync delay) that varies from 0

to 15 ms. After this period has expired, the CS5530 deas-

serts SUSP#, stopping Suspend. SMI# is held active for

the entire period, so that the CPU reenters SMM when the

clocks are restarted.

Note:

The SUSP_3V pin can be active either high or

low. The pin is an input during POR, and is sam-

pled to determine its inactive state. This allows a

designer to match the active state of SUSP_3V to

the inactive state for a clock driver output enable

with a pull-up or pull-down resistor.

The bit formats for the Clock Stop Control Register are

given in Table 3-14.

Table 3-14. Clock Stop Control Register

Bit

Description

F0 Index BCh

Clock Stop Control Register (R/W)

Reset Value = 00h

7:4

PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the

SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before start-

ing execution. This delay is only invoked if the STP_CLK bit (bit 0) was set.

The four-bit field allows values from 0 to 15 ms.

0000 = 0 ms

0100 = 4 ms

1000 = 8 ms

1100 = 12 ms

0001 = 1 ms

0101 = 5 ms

1001 = 9 ms

1101 = 13 ms

0010 = 2 ms

0110 = 6 ms

1010 = 10 ms

1110 = 14 ms

0011 = 3 ms

0111 = 7 ms

1011 = 11 ms

1111 = 15 ms

3:1

Reserved: Set to 0.

CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.

Notes:

This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after

the appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a

delay for the clock chip and CPU PLL to stabilize when an event Resumes the system.

A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as:

0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped.

When a break/resume event occurs, it releases the CPU halt condition.

1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both

CPU and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay pro-

grammed in bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the

SUSP# pin.

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