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Functional Description (Continued)

F0 Index 8Ch

IRQ Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

IRQ Speedup Timer Count: This field represents the load value for the IRQ speedup timer. It is loaded into the counter

when Suspend Modulation is enabled (F0 Index 96[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the

event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expira-

tion, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typi-

cal value here would be 2 to 4 ms.

F0 Index 8Dh

Video Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

Video Speedup Timer Count: This field represents the load value for the Video speedup timer. It is loaded into the

counter when Suspend Modulation is enabled (F0 Index 96[0] = 1) and any access to the graphics controller occurs.

When a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the

CPU. Upon expiration, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase

is 1 ms.

This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-

tions. A typical value here would be 50 to 100 ms.

F0 Index 94h

Suspend Modulation OFF Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Deasserted Count: This 8-bit counter represents the number of 32 µs intervals that the SUSP#

pin is deasserted to the processor. This counter, together with the Suspend Modulation ON Count Register (F0 Index

95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an

effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption.

This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

F0 Index 95h

Suspend Modulation ON Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Asserted Count: This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin is

asserted. This counter, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend

Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock

frequency, allowing the power manager to reduce CPU power consumption.

This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

F0 Index 96h

Suspend Configuration Register (R/W)

Reset Value = 00h

7:3

Reserved: Set to 0.

Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down the GXLV processor during

Suspend: 0 = Disable; 1 = Enable.

SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs:

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI

occurs.

1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory

Offset 08h).

The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA

and Power Management operations occur at full speed. Two methods for accomplishing this are either to map the SMI

into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI

handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The

IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if

the Suspend Modulation feature is disabled (bit 0 = 0).

Suspend Modulation Feature Enable: Suspend Modulation feature: 0 = Disable; 1 = Enable.

When enabled, the SUSP# pin is asserted and deasserted for the durations programmed in the

Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h).

F0 Index A8h-A9h

Video Overflow Count Register (R/W)

Reset Value = 0000h

15:0

Video Overflow Count: Each time the Video Speedup Counter (F0 Index 8Dh) is triggered, a 100 ms timer is started. If

the 100 ms timer expires before the Video Speedup Counter lapses, the Video Overflow Count Register increments and

the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count con-

tained in this register may be combined with other data to determine the type of video accesses present in the system.

Table 3-13. Suspend Modulation Related Registers (Continued)

Bit

Description

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