CS5530 datasheet(95/241 Pages) NSC

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Functional Description (Continued)

PIT Registers

The PIT registers are summarized and bit formats are in

Table 4-27 "Programmable Interval Timer Registers" on

page 212.

PIT Shadow Register

The PIT registers are shadowed to allow for Zero Volt

Suspend to save/restore the PIT state by reading the PITs

counter and write-only registers. The read sequence for

the shadow register is listed in F0 Index BAh, Table 3-41.

3.5.4.3

Programmable Interrupt Controller

The CS5530 includes an AT-compatible Programmable

Interrupt Controller (PIC) configuration with two 8259-

equivalent interrupt controllers in a master/slave configu-

ration (Figure 3-15).

Figure 3-15. PIC Interrupt Controllers

IR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

INTR

Processor

8254 Timer 0

RTC_IRQ#

INTR

IR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Table 3-41. PIT Shadow Register

Bit

Description

F0 Index BAh

PIT Shadow Register (RO)

Reset Value = xxh

7:0

PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer

registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A

write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last

data written to that location.

The read sequence for this register is:

1. Counter 0 LSB (least significant byte)

2. Counter 0 MSB

3. Counter 1 LSB

4. Counter 1 MSB

5. Counter 2 LSB

6. Counter 2 MSB

7. Counter 0 Command Word

8. Counter 1 Command Word

9. Counter 2 Command Word

Note: The LSB/MSB of the count is the Counter base value, not the current value.

Bits [7:6] of the command words are not used.

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