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CS5530 数据表(PDF) 52 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 52 Page - National Semiconductor (TI) |
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52 / 241 page  www.national.com 52 Revision 4.1 Functional Description (Continued) Table 3-9. DCLK Configuration Register Bit Description F4BAR+Memory Offset 24h-27h DOT Clock Configuration Register (R/W) Reset Value = 00000000h 31 Reset: Reset the PLL: 0 = Normal operation; 1 = Reset 30 Half Clock: 0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle. 29 Reserved: Set to 0. 28:24 5-Bit DCLK PLL Post Divisor (PD) Value: Selects value of 1 to 31: 00000 = PD divisor of 8 01000 = PD divisor of 10 10000 = PD divisor of 9 11000 = PD divisor of 11 00001 = PD divisor of 6 01001 = PD divisor of 20 10001 = PD divisor of 7 11001 = PD divisor of 21 00010 = PD divisor of 18 01010 = PD divisor of 14 10010 = PD divisor of 19 11010 = PD divisor of 15 00011 = PD divisor of 4 01011 = PD divisor of 26 10011 = PD divisor of 5 11011 = PD divisor of 27 00100 = PD divisor of 12 01100 = PD divisor of 22 10100 = PD divisor of 13 11100 = PD divisor of 23 00101 = PD divisor of 16 01101 = PD divisor of 28 10101 = PD divisor of 17 11101 = PD divisor of 29 00110 = PD divisor of 24 01110 = PD divisor of 30 10110 = PD divisor of 25 11110 = PD divisor of 31 00111 = PD divisor of 2 01111 = PD divisor of 1* 10111 = PD divisor of 3 11111 = RSVD *See bit 11 description. 23 Plus 1 (+1): Adds 1 or 0 to FD (DCLK PLL VCO Feedback Divisor) parameter in equation (see Note): 0 = Add0 to FD; 1 = Add 1toFD 22:12 N: This bit represents “N” in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO Feedback Divi- sor). N can be a value of 1 to 400. For all values of N, refer to Table 3-10. 11 CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled. 10 Reserved: Set to 0. 9 Select Feedback Source: 0 = DPLL; 1 = FREF. 8 Bypass PLL: Connects the input of the PLL directly to the output of the PLL: 0 = Normal Operation; 1 = Bypass PLL. If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down the PLL. Allow 0.5 ms for the control voltage to be driven to 0V. 7:6 Reserved: Set to 0. 5 PLL Lock Indicator: 0 = PLL has not locked on frequency; 1 = PLL has locked on frequency. 4:3 Reserved: Set to 0. 2:0 PLL Input Divide (ID) Value: Selects value of 2 to 9 (see Note): 000 = ID divisor of 2 100 = ID divisor of 6 001 = ID divisor of 3 101 = ID divisor of 7 010 = ID divisor of 4 110 = ID divisor of 8 011 = ID divisor of 5 111 = ID divisor of 9 Note: To calculate DCLK output frequency: Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID] Condition: 140 MHz < [DCLK * PD] < 300 MHz Where: CLK_14MHZ is pin P24 FD is derived from N see equation #2 and #3: PD is derived from bits [28:24] ID is derived from bits [2:0] Equation #2: If FD is an odd number then: FD = 2*N +1 Equation #3: If FD is an even number then: FD = 2*N +0 Where: N is derived from bits [22:12] +1 is achieved by setting bit 23 to 1. +0 s achieved by clearing bit 23 to 0. |
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