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CS5530 数据表(PDF) 84 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 84 Page - National Semiconductor (TI) |
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84 / 241 page ![]() www.national.com 84 Revision 4.1 Functional Description (Continued) 3.5 PC/AT COMPATIBILITY LOGIC The CS5530’s PC/AT compatibility logic provides support for the standard PC architecture. This subsystem also provides legacy support for existing hardware and soft- ware. Support functions for the GXLV processor provided by these subsystems include: • ISA Subtractive Decode • ISA Bus Interface - Delayed PCI Transactions - Limited ISA and ISA Master Modes • ROM Interface • Megacells - Direct Memory Access (DMA) - Programmable Interval Timer - Programmable Interrupt Controller - PCI Compatible Interrupts - System Control I/O Port 092h and 061h - Keyboard Interface Function - External Real-Time Clock Interface The following subsections give a detailed description for each of these functions. 3.5.1 ISA Subtractive Decode The CS5530 provides an ISA bus controller. The CS5530 is the default subtractive-decoding agent, and forwards all unclaimed memory and I/O cycles to the ISA interface. However, the CS5530 can be configured using F0 Index 04h[1:0] to ignore either I/O, memory, or all unclaimed cycles (subtractive decode disabled, F0 Index 41h[2:1] = 1x (Table 3-35). Table 3-35. Cycle Configuration Bits Bit Description F0 Index 04h-05h PCI Command Register (R/W) Reset Value = 0000h 1 Memory Space: Allow the CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable (Default). 0 I/O Space: Allow the CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable (Default). F0 Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 2:1 Subtractive Decode: These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode |
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