CS5530 datasheet(10/241 Pages) NSC

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Revision 4.1

Architecture Overview (Continued)

1.8

CLOCK GENERATION

In a CS5530/GXLV processor-based system, the CS5530

generates only the video DOT clock (DCLK) for the CPU

and the ISA clock. All other clocks are generated by an

external clock chip.

The ISACLK is created by dividing the PCICLK. For ISA

compatibility, the ISACLK nominally runs at 8.33 MHz or

less. The ISACLK dividers are programmed via F0 Index

50h[2:0].

DCLK is generated from the 14.31818 MHz input

(CLK_14MHZ). A combination of a phase locked loop

(PLL), linear feedback shift register (LFSR) and divisors

are used to generate the desired frequencies for the

DCLK. The divisors and LFSR are configurable through

the F4BAR+Memory Offset 24h. For applications that do

not use the GXLV processor’s video, this is an available

clock for general purpose use.

Figure 1-4 shows a block diagram for clock generation

within the CS5530.

Figure 1-4. CS5530 Clock Generation

1.9

UNIVERSAL SERIAL BUS

The CS5530 provides two complete, independent USB

ports. Each port has a Data "–" and a Data "+" pin.

The USB controller is a compliant Open Host Controller

Interface (OpenHCI). The OpenHCI specification provides

a register-level description for a host controller, as well as

a common industry hardware/software interface and driv-

ers (see OpenHCI Specification, Revision 1.0, for descrip-

tion).

DCLK

PLL

÷N

TVCLK

CLK_14MHZ

ISACLK

PCICLK

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