CS5530 datasheet(73/241 Pages) NSC

73 / 241 page

Revision 4.1

www.national.com

Functional Description (Continued)

3.4.3.4

General Purpose I/O Pins

The CS5530 provides up to eight GPIO (general purpose

I/O) pins. Five of the pins (GPIO[7:4] and GPIO1) have

alternate functions. Table 3-30 shows the bits used for

GPIO pin function selection.

Each GPIO pin can be configured as an input or output.

GPIO[7:0] can be independently configured to act as

edge-sensitive SMI events. Each pin can be enabled and

configured to be either positive-edge sensitive or nega-

tive-edge sensitive. These pins then cause an SMI to be

generated when an appropriate edge condition is

detected. The power management status registers indi-

cate that a GPIO external SMI event has occurred.

The GPIO Pin Direction Register 1 (F0 Index 90h) selects

whether the GPIO pin is an input or output. The GPIO Pin

Data Register 1 (F0 Index 91h) contains the direct values

of the GPIO pins. Write operations are valid only for bits

defined as output. Reads from this register will read the

last written value if the pin is an output.

GPIO Control Register 1 (F0 Index 92h) configures the

operation of the GPIO pins for their various alternate func-

tions. Bits [5:3] set the edge sensitivity for generating an

SMI on the GPIO[2:0] (input) pins respectively. Bits [2:0]

enable the generation of an SMI. Bit 6 enables GPIO6 to

act as the lid switch input. Bit 7 determines which edge

transition will cause the General Purpose Timer 2 (F0

Index 8Ah) to reload.

Table 3-31 shows the bit formats for the GPIO pin configu-

ration and control registers.

Table 3-30. GPIO Pin Function Selection

Bit

Description

F0 Index 43h

USB Shadow Register (R/W)

Reset Value = 03h

Enable SA20: Pin AD22 configuration: 0 = GPIO4; 1 = SA20. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 =

SA20.

Enable SA[23:20]: Pins AF23, AE23, AC21, and AD22 configuration: 0 = GPIO[7:4]; 1 = SA[23:20]. If F0 Index 43h bit 6

or bit 2 is set to 1, then pin AD22 = SA20.

F3BAR+Memory Offset 08h-0Bh

Codec Status Register (R/W)

Reset Value = 00000000h

Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2.

For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0).

Table 3-31. GPIO Pin Configuration/Control Registers

Bit

Description

F0 Index 90h

GPIO Pin Direction Register 1 (R/W)

Reset Value = 00h

GPIO7 Direction: Selects if GPIO7 is an input or output: 0 = Input; 1 = Output.

GPIO6 Direction: Selects if GPIO6 is an input or output: 0 = Input; 1 = Output.

GPIO5 Direction: Selects if GPIO5 is an input or output: 0 = Input; 1 = Output.

GPIO4 Direction: Selects if GPIO4 is an input or output: 0 = Input; 1 = Output.

GPIO3 Direction: Selects if GPIO3 is an input or output: 0 = Input; 1 = Output.

GPIO2 Direction: Selects if GPIO2 is an input or output: 0 = Input; 1 = Output.

GPIO1 Direction: Selects if GPIO1 is an input or output: 0 = Input; 1 = Output.

GPIO0 Direction: Selects if GPIO0 is an input or output: 0 = Input; 1 = Output.

Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins’ use as

the alternate function.

F0 Index 91h

GPIO Pin Data Register 1 (R/W)

Reset Value = 00h

GPIO7 Data: Reflects the level of GPIO7: 0 = Low; 1 = High.

GPIO6 Data: Reflects the level of GPIO6: 0 = Low; 1 = High.

GPIO5 Data: Reflects the level of GPIO5: 0 = Low; 1 = High.

GPIO4 Data: Reflects the level of GPIO4: 0 = Low; 1 = High.

GPIO3 Data: Reflects the level of GPIO3: 0 = Low; 1 = High.

GPIO2 Data: Reflects the level of GPIO2: 0 = Low; 1 = High.

GPIO1 Data: Reflects the level of GPIO1: 0 = Low; 1 = High.

GPIO0 Data: Reflects the level of GPIO0: 0 = Low; 1 = High.

Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from

this register will read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h.

CS5530 数据表(PDF) 73 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 73 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载