CS5530 datasheet(77/241 Pages) NSC

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Functional Description (Continued)

Table 3-32. Top Level SMI Status Register (Read to Clear)

Bit

Description

F1BAR+Memory Offset 02h-03h

Top Level SMI Status Register (RC)

Reset Value = 0000h

Suspend Modulation Enable Mirror (Read to Clear): This bit mirrors the Suspend Modulation Feature Enable bit (F0

Index 96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset

08h) must be cleared on exit.

SMI Source is USB (Read to Clear): SMI was caused by USB activity? 0 = No; 1 = Yes.

SMI generation is configured in F0 Index 42h[7:6].

SMI Source is Warm Reset Command (Read to Clear): SMI was caused by Warm Reset command?

0= No; 1 = Yes.

SMI Source is NMI (Read to Clear): SMI was caused by NMI activity? 0 = No; 1 = Yes.

11:10

Reserved (Read to Clear): Always reads 0.

SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read to Clear): SMI was

caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register

Space? 0 = No; 1 = Yes.

The next level of status is found at F1BAR+Memory Offset 04h/06h.

SMI Source is Software Generated (Read to Clear): SMI was caused by software? 0 = No; 1 = Yes.

SMI on an A20M# Toggle (Read to Clear): SMI was caused by an access to either Port 092h or the keyboard command

which initiates an A20M# SMI? 0 = No; 1 = Yes.

This method of controlling the internal A20M# in the GXLV processor is used instead of a pin.

SMI generation enabling is at F0 Index 53h[0].

SMI Source is a VGA Timer Event (Read to Clear): SMI was caused by the expiration of the VGA Timer

(F0 Index 8Eh)? 0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[3].

SMI Source is Video Retrace (IRQ2) (Read to Clear): SMI was caused by a video retrace event as decoded from the

serial connection (PSERIAL register, bit 7) from the GXLV processor? 0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[2].

4:2

Reserved (Read to Clear): Always reads 0.

SMI Source is Audio Interface (Read to Clear): SMI was caused by the audio interface? 0 = No; 1 = Yes.

The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h.

SMI Source is Power Management Event (Read to Clear): SMI was caused by one of the power management

resources? 0 = No; 1 = Yes.

The next level of status is found at F0 Index 84h-87h/F4h-F7h.

Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.

Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting.

A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read with-

out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

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