CS5530 datasheet(48/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.2.5

PCI Interrupt Routing Support

The CS5530 allows the PCI interrupt signals INTA#,

INTB#, INTC#, and INTD# (also know in industry terms as

PIRQx#) to be mapped internally to any IRQ signal via

are supplied in Section 3.5.4.4 “PCI Compatible Inter-

rupts” on page 98 regarding edge/level sensitivity selec-

tion.

3.2.6

Delayed Transactions

The CS5530 supports delayed transactions to prevent

slow PCI cycles from occupying too much bandwidth and

allows access for other PCI traffic.

Note:

For systems which have only the GXLV processor

and CS5530 on the PCI bus, system performance

is improved if delayed transactions are disabled.

F0 Index 42h[5] and F0 Index 43h[1] are used to program

this function. Table 3-7 shows these bit formats.

Table 3-6. PCI Interrupt Steering Registers

Bit

Description

F0 Index 5Ch

PCI Interrupt Steering Register 1 (R/W)

Reset Value = 00h

7:4

INTB# Target Interrupt: Selects target interrupt for INTB#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTA# Target Interrupt: Selects target interrupt for INTA#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

‘

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI

interrupt compatibility

F0 Index 5Dh

PCI Interrupt Steering Register 2 (R/W)

Reset Value = 00h

7:4

INTD# Target Interrupt: Selects target interrupt for INTD#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTC# Target Interrupt: Selects target interrupt for INTC#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI

interrupt compatibility

Table 3-7. Delay Transaction Programming Bits

Bit

Description

F0 Index 42h

PCI Function Control Register 3 (R/W)

Reset Value = ACh

Delayed Transactions: Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable.

Also see F0 Index 43h[1].

F0 Index 43h

USB Shadow Register (R/W)

Reset Value = 03h

PCI Retry Cycles: When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles:

0 = Disable; 1 = Enable.

This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid.

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