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CS5530 数据表(PDF) 37 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 37 Page - National Semiconductor (TI) |
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37 / 241 page  Revision 4.1 37 www.national.com Signal Definitions (Continued) FP_VSYNC C1 I Limited ISA Mode: Flat Panel Vertical Sync Input This is the vertical sync input reference from the processor’s display con- troller. The timing of this signal is independent of the standard (CRT) verti- cal sync input to allow a different timing relationship between the flat panel andanattached CRT. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_VSYNC_OUT /SMEMR# E3 O Limited ISA Mode: Flat Panel Vertical Sync Output This is the vertical sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel vertical sync signal with the appropriate pipeline delay relative to the pixel data. ISA Master Mode: System Memory Read Refer to Section 2.2.5 “ISA Bus Interface” on page 28 for this signal’s def- inition. FP_DISP_ ENA_OUT F2 O Flat Panel Display Enable Output This is the display enable for an attached active matrix TFT flat panel. This signal qualifies active pixel data on the flat panel interface. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_ENA_VDD L2 O Flat Panel VDD Enable This is the enable signal for the VDD supply to an attached flat panel. It is under the control of power sequence control logic. A transition on bit 6 of the Display Configuration Register (F4BAR+Memory Offset 04h) initiates a power-up/down sequence. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. FP_ENA_BKL J4 O Flat Panel Backlight Enable Output This is the enable signal for the backlight power supply to an attached flat panel. It is under control of the power sequence control logic. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530 can not support TFT flat panels or TV controllers. Display MPEG VID_DATA[7:0] C12, B12, A12, D11, C11, B13, C13, A11 I Video Data Port This is the input data for a video (MPEG) or graphics overlay in its native form. For video overlay, this data is in an interleaved YUV 4:2:2 format. For graphics overlay, the data is in RGB 5:6:5 format. This port operates at the VID_CLK rate. 2.2.11 Display Interface (Continued) Signal Name Pin No. Type Description |
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