CS5530 datasheet(98/241 Pages) NSC

98 / 241 page

www.national.com

Revision 4.1

Functional Description (Continued)

3.5.4.4

PCI Compatible Interrupts

The CS5530 allows the PCI interrupt signals INTA#,

INTB#, INTC#, and INTD# (also known in industry terms

as PIRQx#) to be mapped internally to any IRQ signal

with the PCI Interrupt Steering Registers 1 and 2, F0

Index 5Ch and 5Dh (Table 3-45).

PCI interrupts are low-level sensitive, whereas PC/AT

interrupts are positive-edge sensitive; therefore, the PCI

interrupts are inverted before being connected to the

8259.

Although the controllers default to the PC/AT-compatible

mode (positive-edge sensitive), each IRQ may be individ-

ually programmed to be edge or level sensitive using the

Interrupt Edge/Level Sensitivity registers in I/O Port 4D0h

and 4D1h, as shown in Table 3-46. However, if the control-

lers are programmed to be level-sensitive via ICW1, all

interrupts must be level-sensitive. Figure 3-16 shows the

PCI interrupt mapping for the master/slave 8259 interrupt

controller.

Figure 3-16. PCI and IRQ Interrupt Mapping

PCI INTA#-INTD#

IRQ[15:14,12:9,7:3,1]

Steering Registers

F0 Index 5Ch,5Dh

ICW1

4D0h/4D1h

MASTER/SLAVE

8259 PIC

INTR

IRQ[13,8,0]

Level/Edge

IRQ3

IRQ4

IRQ15

Sensitivity

Table 3-45. PCI Interrupt Steering Registers

Bit

Description

F0 Index 5Ch

PCI Interrupt Steering Register 1 (R/W)

Reset Value = 00h

7:4

INTB# Target Interrupt:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTA# Target Interrupt:

0000 = Disable

0100 = IRQ4

1000 = RSVD

‘

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt

compatibility

F0 Index 5Dh

PCI Interrupt Steering Register 2 (R/W)

Reset Value = 00h

7:4

INTD# Target Interrupt:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTC# Target Interrupt:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt

compatibility

CS5530 数据表(PDF) 98 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 98 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5530 数据表(PDF) 98 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 98 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载