CS5530 datasheet(101/241 Pages) NSC

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Functional Description (Continued)

3.5.5.1

I/O Port 092h System Control

I/O Port 092h allows for a fast keyboard assertion of an

A20# SMI and a fast keyboard CPU reset. Decoding for

this register may be disabled via F0 Index 52h[3] (Table 3-

48).

The assertion of a fast keyboard A20# SMI is controlled

by either I/O Port 092h or by monitoring for the keyboard

command sequence (see Section 3.5.6.1 “Fast Keyboard

Gate Address 20 and CPU Reset” on page 103). If bit 1 of

I/O Port 092h is cleared, the CS5530 internally asserts an

A20M# SMI, which in turn causes an SMI to the proces-

sor. If bit 1 is set, A20M# SMI is internally deasserted

again causing an SMI.

The assertion of a fast keyboard reset (WM_RST SMI) is

controlled by bit 0 in I/O Port 092h or by monitoring for the

keyboard command sequence. If bit 0 is changed from a 0

to a 1, the CS5530 generates a reset to the processor by

generating a WM_RST SMI. When the WM_RST SMI

occurs, the BIOS jumps to the Warm Reset vector. This bit

remains set until the CS5530 is externally reset, or this bit

is cleared by program control. Note that Warm Reset is

not a pin, it is under SMI control.

3.5.5.2

I/O Port 061h System Control

Through I/O Port 061h, the speaker output can be

enabled, NMI from IOCHK# or SERR# can be enabled,

thestatusofIOCHK#and SERR# canberead, and the

state of the speaker data (Timer2 output) and refresh tog-

gle (Timer1 output) can be read back. Note that NMI is

under SMI control.

3.5.5.3

SMI Generation for NMI

Figure 3-17 shows how the CS5530 can generate an SMI

for an NMI. Note that NMI is not a pin.

Figure 3-17. SMI Generation for NMI

Table 3-48. I/O Port 092h Decode Enable Bit

Bit

Description

F0 Index 52h

ROM/AT Logic Control Register (R/W)

Reset Value = F8h

Enable Port 092h Decode (Port A): I/O Port 092h decode and the logical functions: 0 = Disable; 1 = Enable.

PERR#

IOCHK#

F0 Index 04h[6]

SERR#

F0 Index 04h[8]

F0 Index 41h[5]

I/O Port 061h[2]

I/O Port 061h[3]

I/O Port 070h[7]

Parity Errors

AND

System Errors

NMI

SMI

F0 Index 04h: PCI Command Register

Bit 6 = PE (Parity Error Enable)

Bit 8 = SERR# (SERR# Enable)

F0 Index 41h: PCI Function Control Register 2

Bit 5 = PES (PERR# Signals SERR#)

I/O Port 061h: Port B

Bit 2 = ERR_EN (PERR#/SERR# enable)

Bit 3 = IOCHK_EN (IOCHK Enable)

I/O Port 070h: RTC Index Register (WO)

Bit 7 = NMI (NMI Enable)

AND

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