CS5530 datasheet(104/241 Pages) NSC

104 / 241 page

www.national.com

104

Revision 4.1

Functional Description (Continued)

3.5.7

External Real-Time Clock Interface

I/O Ports 070h and 071h decodes are provided to inter-

face to an external real-time clock controller. I/O Port

070h, a write only port, is used to set up the address of

the desired data in the controller. This causes the address

to be placed on the ISA data bus, and the RTCALE signal

to be triggered. A read of I/O Port 071h causes an ISA I/O

read cycle to be performed while asserting the RTCCS#

signal.A writetoI/O Port 071hcausesanISA I/O write

cycle to be performed with the desired data being placed

on theISA busand theRTCCS#signaltobeasserted.

RTCCS#/SMEMW# and RTCALE/SMEMR# are multi-

plexed pins. The function selection is made through F0

Index 53h[2].

The connection between the CS5530 and an external

real-time clock is shown in Figure 3-18.

The CS5530 also provides the RTC Index Shadow Regis-

ter (F0 Index BBh) to store the last write to I/O Port 070h.

Table 3-52 shows the bit formats for the associated regis-

ters for interfacing with an external real-time clock.

Figure 3-18. External RTC interface

SD[7:0]

RTCALE/SMEMR#

IOR#

IOW#

RTC

RTCCS#/SMEMW#

IRQ8#

Table 3-52. Real-Time Clock Registers

Bit

Description

I/O Port 070h

RTC Address Register (WO)

NMI Mask: 0 = Enable; 1 = Mask.

6:0

RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be

triggered.

Note: This register is shadowed within the CS5530 and is read through the RTC Shadow Register (F0 Index BBh).

I/O Port 071h

RTC Data Register (R/W)

A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#.

A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#.

F0 Index BBh

RTC Index Shadow Register (RO)

Reset Value = xxh

7:0

RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index

F0 Index 53h

Alternate CPU Support Register (R/W)

Reset Value = 00h

RTC Enable and RTC Pin Configuration: 0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled

1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled.

Note: Shadow register is independent of the enable register.

CS5530 数据表(PDF) 104 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 104 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载