CS5530 datasheet(106/241 Pages) NSC

106 / 241 page

www.national.com

106

Revision 4.1

Functional Description (Continued)

3.6.2

IDE Configuration Registers

Registers for configuring the IDE interface are accessed

through F2 Index 20h, the Base Address Register

(F2BAR) in Function 2. F2BAR sets the base address for

the IDE Controllers Configuration Registers as shown in

Table 3-54. For complete bit information, refer to Section

4.3.3 “IDE Controller Registers - Function 2” on page 184.

The

following

subsections

discuss

CS5530

opera-

tional/programming details concerning PIO, Bus Master,

and Ultra DMA/33 modes.

3.6.2.1

PIO Mode

The IDE data port transaction latency consists of address

latency, asserted latency and recovery latency. Address

latency occurs when a PCI master cycle targeting the IDE

data port is decoded, and the IDE_ADDR[2:0] and

IDE_CS# lines are not set up. Address latency provides

the setup time for the IDE_ADDR[2:0] and IDE_CS# lines

prior to IDE_IOR# and IDE_IOW#.

Asserted latency consists of the I/O command strobe

assertion length and recovery time. Recovery time is pro-

vided so that transactions may occur back-to-back on the

IDE interface without violating minimum cycle periods for

the IDE interface.

If IDE_IORDY is asserted when the initial sample point is

reached, no wait states are added to the command strobe

assertion length. If IDE_IORDY is negated when the initial

sample point is reached, additional wait states are added.

Recovery latency occurs after the IDE data port transac-

tions have completed. It provides hold time on the

IDE_ADDR[2:0] and IDE_CS# lines with respect to the

read and write strobes (IDE_IOR# and IDE_IOW#).

The PIO portion of the IDE registers is enabled through:

• Channel 0 Drive 0 Programmed I/O Register

(F2BAR+I/O Offset 20h)

• Channel 0 Drive 1 Programmed I/O Register

(F2BAR+I/O Offset 28h)

• Channel 1 Drive 0 Programmed I/O Register

(F2BAR+I/O Offset 30h)

• Channel 1 Drive 1 Programmed I/O Register

(F2BAR+I/O Offset 38h)

The IDE channels and devices can be individually pro-

grammed to select the proper address setup time,

asserted time, and recovery time.

Thebit formatsfor theseregistersare showninTable3-

55. Note that there are different bit formats for each of the

PIO programming registers depending on the operating

format selected: Format 0 or Format 1.

F2BAR+I/O Offset 24h[31] (Channel 0 Drive 0 — DMA

Control Register) sets the format of the PIO register. If bit

31 = 0, Format 0 is used and it selects the slowest PIO-

MODE (bits [19:16]) per channel for commands. If bit 31 =

1, Format 1 is used and it allows independent control of

command and data.

Also listed in the bit formats are recommended values for

the different PIO modes.

Note:

These are only recommended settings and are

not 100% tested.

Table 3-54. Base Address Register (F2BAR) for IDE Support Registers

Bit

Description

F2 Index 20h-23h

Base Address Register — F2BAR (R/W)

Reset Value = 00000001h

This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001),

indicating a 128 byte I/O address range. Refer to Table 4-18 for the IDE configuration registers bit formats and reset values.

31:7

Bus Mastering IDE Base Address

6:0

Address Range (Read Only)

CS5530 数据表(PDF) 106 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 106 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载