CS5530 datasheet(107/241 Pages) NSC

107 / 241 page

Revision 4.1

107

www.national.com

Functional Description (Continued)

Table 3-55. PIO Programming Registers

Bit

Description

F2BAR+I/O Offset 20h-23h

Channel 0 Drive 0 PIO Register (R/W)

Reset Value = 0000E132h (Note)

If Offset 24h[31] = 0, Format 0: Selects slowest PIOMODE per channel for commands.

Format 0 settings for: PIO Mode 0 = 00009172h

PIO Mode 1 = 00012171h

PIO Mode 2 = 00020080h

PIO Mode 3 = 00032010h

PIO Mode 4 = 00040010h

31:20

Reserved: Set to 0.

19:16

PIOMODE: PIO mode

15:12

t2I: Recovery time (value + 1 cycle)

11:8

t3: IDE_IOW# data setup time (value + 1 cycle)

7:4

t2W: IDE_IOW# width minus t3 (value + 1 cycle)

3:0

t1: Address Setup Time (value + 1 cycle)

If Offset 24h[31] = 1, Format 1: Allows independent control of command and data.

Format 1 settings for: PIO Mode 0 = 9172D132h

PIO Mode 1 = 21717121h

PIO Mode 2 = 00803020h

PIO Mode 3 = 20102010h

PIO Mode 4 = 00100010h

31:28

t2IC: Command cycle recovery time (value + 1 cycle)

27:24

t3C: Command cycle IDE_IOW# data setup (value + 1 cycle)

23:20

t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)

19:16

t1C: Command cycle address setup time (value + 1 cycle)

15:12

t2ID: Data cycle recovery time (value + 1 cycle)

11:8

t3D: Data cycle IDE_IOW# data setup (value + 1 cycle)

7:4

t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)

3:0

t1D: Data cycle address Setup Time (value + 1 cycle)

Note: The reset value of this register is not a valid PIO Mode.

F2BAR+I/O Offset 28h-2Bh

Channel 0 Drive 1 PIO Register (R/W)

Reset Value = 0000E132h

Channel 0 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

F2BAR+I/O Offset 30h-33h

Channel 1 Drive 0 PIO Register (R/W)

Reset Value = 0000E132h

Channel 1 Drive 0 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

F2BAR+I/O Offset 38h-3Bh

Channel 1 Drive 1 PIO Register (R/W)

Reset Value = 0000E132h

Channel 1 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

CS5530 数据表(PDF) 107 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 107 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5530 数据表(PDF) 107 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 107 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载