CS5530 datasheet(111/241 Pages) NSC

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Functional Description (Continued)

3.6.2.3

Ultra DMA/33 Mode

The CS5530 supports Ultra DMA/33. It utilizes the stan-

dard IDE Bus Master functionality to interface, initiate and

control the transfer. Ultra DMA/33 definition also incorpo-

rates a Cyclic Redundancy Checking (CRC) error check-

ing protocol to detect errors.

The Ultra DMA/33 protocol requires no extra signal pins

on the IDE connector. The CS5530 redefines three stan-

dard IDE control signals when in Ultra DMA/33 mode.

These definitions are shown in Table 3-59.

All other signals on the IDE connector retain their func-

tional definitions during the Ultra DMA/33 operation.

IDE_IOW# is defined as STOP for both read and write

transfers to request to stop a transaction.

IDE_IOR# is redefined as DMARDY# for transferring data

from the IDE device to the CS5530. It is used by the

CS5530 to signal when it is ready to transfer data and to

add wait states to the current transaction. IDE_IOR# sig-

nal is defined as STROBE for transferring data from the

CS5530 to the IDE device. It is the data strobe signal

driven by the CS5530 on which data is transferred during

each rising and falling edge transition.

IDE_IORDY is redefined as STROBE for transferring data

from the IDE device to the CS5530 during a read cycle. It

is the data strobe signal driven by the IDE device on which

data is transferred during each rising and falling edge

transition. IDE_IORDY is defined as DMARDY# during a

write cycle for transferring data from the CS5530 to the

IDE device. It is used by the IDE device to signal when it is

ready to transfer data and to add wait states to the current

transaction.

Ultra DMA/33 data transfer consists of three phases, a

startup phase, a data transfer phase and a burst termina-

tion phase.

The IDE device begins the startup phase by asserting

IDE_DREQ. When ready to begin the transfer, the

CS5530 asserts IDE_DACK#. When IDE_DACK# is

asserted, the CS5530 drives IDE_CS0# and IDE_CS1#

asserted, and IDE_ADDR[2:0] low. For write cycles, the

CS5530 negates STOP, waits for the IDE device to assert

DMARDY#, and then drives the first data word and

STROBE signal. For read cycles, the CS5530 negates

STOP, and asserts DMARDY#. The IDE device then

sends the first data word and asserts STROBE.

The data transfer phase continues the burst transfers with

the CS5530 and the IDE via providing data, toggling

STROBE and DMARDY#. The IDE_DATA[15:0] is latched

by receiver on each rising and falling edge of STROBE.

The transmitter can pause the burst cycle by holding

STROBE high or low, and resume the burst cycle by again

toggling STROBE. The receiver can pause the burst cycle

by negating DMARDY# and resumes the burst cycle by

asserting DMARDY#.

The current burst cycle can be terminated by either the

transmitter or the receiver. A burst cycle must first be

paused as described above before it can be terminated.

TheCS5530 canthenstopthe burstcycle by asserting

STOP, with the IDE device acknowledging by negating

IDE_DREQ. The IDE device then stops the burst cycle by

negating IDE_DREQ and the CS5530 acknowledges by

assertingSTOP. Thetransmitter then drivesthe STROBE

signal to a high level. The CS5530 then puts the result of

the CRC calculation onto the IDE_DATA[15:0] while deas-

serting IDE_DACK#. The IDE device latches the CRC

value on the rising edge of IDE_DACK#.

The CRC valueisusedfor errorchecking onUltra

DMA/33 transfers. The CRC value is calculated for all

data by both the CS5530 and the IDE device during the

Ultra DMA/33 burst transfer cycles. This result of the CRC

calculation is defined as all data transferred with a valid

STROBE edge while IDE_DACK# is asserted. At the end

of the burst transfer, the CS5530 drives the result of the

CRC calculation onto IDE_DATA[15:0] which is then

strobed by the deassertion of IDE_DACK#. The IDE

device compares the CRC result of the CS5530 to its own

and reports an error if there is a mismatch.

The timings for Ultra DMA/33 are programmed into the

DMA control registers:

• Channel 0 Drive 0 DMA Control Register (F2BAR+I/O

Offset 24h)

• Channel 0 Drive 1 DMA Control Register (F2BAR+I/O

Offset 2Ch)

• Channel 1 Drive 0 DMA Control Register (F2BAR+I/O

Offset 34h)

• Channel 1 Drive 1 DMA Control Register (F2BAR+I/O

Offset 3Ch)

The bit formats for these registers are given in Table 3-60.

Note that F2BAR+I/O Offset 24h[20] is used to select

either Multiword or Ultra DMA mode. Bit 20 = 0 selects

Multiword DMA mode. If bit 20 = 1, then Ultra DMA/33

mode is selected. Once mode selection is made using this

bit, the remaining DMA Control Registers also operate in

the selected mode.

Also listed in the bit formats are recommended values for

both Multiword DMA Modes 0-2 and Ultra DMA/33 Modes

0-2.

Note:

These are only recommended settings and are

not 100% tested.

Table 3-59. Ultra DMA/33 Signal Definitions

CS5530 IDE

Channel Signal

Ultra DMA/33

Read Cycle

Ultra DMA/33

Write Cycle

IDE_IOW#

STOP

IDE_IOR#

DMARDY#

STROBE

IDE_IORDY

STROBE

DMARDY#

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