CS5530 datasheet(115/241 Pages) NSC

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Functional Description (Continued)

For example, Audio Bus Master 0 is defined as an output

only, so bit 3 of Audio Bus Master 0 Command Register

(F3BAR+Memory Offset 20h[3]) must always be set to 1.

Table 3-62 explains the generic format for the six audio

bus masters. Table 3-63 gives the register locations, reset

values and specific programming information of bit 3,

Read or Write Control, in the Command Register for the

Audio Bus Masters.

Table 3-63. Audio Bus Master Configuration Register Summary

Bit

Description

Audio Bus Master 0: Output to Codec; 32-Bit; Left and Right Channels; Slots 3 and 4.

F3BAR+Memory Offset 20h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 21h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 22h-23h

Not Used

F3BAR+Memory Offset 24h-27h

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active.

Audio Bus Master 1: Input from Codec; 32-Bit; Left and Right Channels; Slots 3 and 4.

F3BAR+Memory Offset 28h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 29h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 2Ah-2Bh

Not Used

F3BAR+Memory Offset 2Ch-2Fh

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active.

Audio Bus Master 2: Output to Codec; 16-Bit; Slot 5

F3BAR+Memory Offset 30h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 31h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 32h-33h

Not Used

F3BAR+Memory Offset 34h-37h

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active.

Audio Bus Master 3: Input from Codec; 16-Bit; Slot 5.

F3BAR+Memory Offset 38h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 39h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 3Ah-3Bh

Not Used

F3BAR+Memory Offset 3Ch-3Fh

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active.

Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot).

F3BAR+Memory Offset 40h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 41h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 42h-43h

Not Used

F3BAR+Memory Offset 44h-47h

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 0 (read) and should not be changed when the bus master is active.

Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot).

F3BAR+Memory Offset 48h

Command Register (R/W)

Reset Value = 00h

F3BAR+Memory Offset 49h

SMI Status Register (RC)

Reset Value = 00h

F3BAR+Memory Offset 4Ah-4Bh

Not Used

F3BAR+Memory Offset 4Ch-4Fh

PRD Table Address (R/W)

Reset Value = 00000000h

Refer to Table 3-62 for bit descriptions.

Note: Bit 3 of the Command Register must be set to 1 (write) and should not be changed when the bus master is active.

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