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CS5530 数据表(PDF) 119 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 119 Page - National Semiconductor (TI) |
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119 / 241 page  Revision 4.1 119 www.national.com Functional Description (Continued) Table 3-65. Codec Configuration/Control Registers Bit Description F3BAR+Memory Offset 00h-03h Codec GPIO Status Register (R/W) Reset Value = 00000000h 31 Codec GPIO Interface: 0 = Disable; 1 = Enable. 30 Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset10h/12h[1]. 29:21 Reserved: Set to 0. 20 Codec GPIO Status Valid (Read Only): Is the status read valid? 0 = Yes; 1 = No. 19:0 Codec GPIO Pin Status (Read Only): This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN signal. F3BAR+Memory Offset 04h-07h Codec GPIO Control Register (R/W) Reset Value = 00000000h 31:20 Reserved: Set to 0. 19:0 Codec GPIO Pin Data: This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal. F3BAR+Memory Offset 08h-0Bh Codec Status Register (R/W) Reset Value = 00000000h 31:24 Codec Status Address (Read Only): Address of the register for which status is being returned. This address comes from slot 1 bits [19:12]. 23 Codec Serial INT SMI: Allow codec serial interrupt to generate an SMI: 0 = Disable; 1= Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset10h/12h[1]. 22 SYNC Pin: Selects SYNC pin level: 0 = Low; 1 = High. 21 Enable SDATA_IN2: Pin AE24 functions as: 0 = GPIO1; 1 = SDATA_IN2. For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). 20 Audio Bus Master 5 AC97 Slot Select: Selects slot for Audio Bus Master 5 to receive data: 0 = Slot 6; 1 = Slot 11. 19 Audio Bus Master 4 AC97 Slot Select: Selects slot for Audio Bus Master 4 to transmit data: 0 = Slot 6; 1 = Slot 11. 18 Reserved: Set to 0. 17 Status Tag (Read Only): Determines if the status in bits [15:0] is new or not: 0 = Not new; 1 = New. 16 Codec Status Valid (Read Only): Is thestatus in bits [15:0] valid?0 =No; 1= Yes. 15:0 Codec Status (Read Only): This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits [19:4] are used from slot 2. F3BAR+Memory Offset 0Ch-0Fh Codec Command Register (R/W) Reset Value = 00000000h 31:24 Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530 Codec Communication: Selects which codec to communicate with: 00 = Primary codec 10 = Third codec 01 = Secondary codec 11 = Fourth codec Note: 00 and 01 are the only valid settings for these bits. 21:17 Reserved: Set to 0. 16 Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Yes. This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec. 15:0 Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT. |
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