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Functional Description (Continued)

Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear)

Bit

Description

F1BAR+Memory Offset 06h-07h

Second Level General Traps/Timers

Reset Value = 0000h

SMI Status Register (RC)

15:6

Reserved (Read to Clear)

PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration cycle (listed below)?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

Trapped Access to F1 Register Space; SMI generation enabling is at F0 Index 41h[3].

Trapped Access to F2 Register Space; SMI generation enabling is at F0 Index 41h[6].

Trapped Access to F3 Register Space; SMI generation enabling is at F0 Index 42h[0].

Trapped Access to F4 Register Space; SMI generation enabling is at F0 Index 42h[1].

Trapped Access to ISA Legacy I/O Register Space; SMI generation enabling is at F0 Index 41h[0].

SMI Source is Trapped Access to User Defined Device 3 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[6].

SMI Source is Trapped Access to User Defined Device 2 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[5].

SMI Source is Trapped Access to User Defined Device 1 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[4].

SMI Source is Expired General Purpose Timer 2 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[1].

SMI Source is Expired General Purpose Timer 1 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[0].

Note: Reading this register clears all the SMI status bits.

A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read with-

out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

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