CS5530 datasheet(92/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.5.4.1

Direct Memory Access (DMA)

The 8237-compatible DMA controllers on the CS5530

control transfers between ISA I/O devices and PCI or ISA

memory. They generate a bus request to the PCI bus

when an I/O device requests a DMA operation. Once they

are granted the bus, the DMA transfer cycle occurs. DMA

transfers can occur over the entire 32-bit address range of

the PCI bus.

The CS5530 contains registers for driving the high

address bits (high page) and registers for generating the

middle address bits (low page) output by the 8237 control-

ler.

DMA Controllers

The CS5530 supports seven DMA channels using two

standard 8237-equivalent controllers. DMA Controller 1

contains Channels 0 through 3 and supports 8-bit I/O

adapters. These channels are used to transfer data

between 8-bit peripherals and PCI memory or 8/16-bit ISA

memory. Using the high and low page address registers, a

full 32-bit PCI address is output for each channel so they

can all transfer data throughout the entire 4 GB system

address space. Each channel can transfer data in 64 KB

pages.

DMA Controller 2 contains Channels 4 through 7. Chan-

nel 4 is used to cascade DMA Controller 1, so it is not

available externally. Channels 5 through 7 support 16-bit

I/O adapters to transfer data between 16-bit I/O adapters

and 16-bit system memory. Using the high and low page

address registers, a full 32-bit PCI address is output for

each channel so they can all transfer data throughout the

entire 4 GB system address space. Each channel can

transfer data in 128 KB pages. Channels 5, 6, and 7 trans-

fer 16-bit words on even byte boundaries only.

DMA Transfer Modes

Each DMA channel can be programmed for single, block,

demand or cascade transfer modes. In the most com-

monly used mode, single transfer mode, one DMA cycle

occurs per DRQ and the PCI bus is released after every

cycle. This allows the CS5530 to timeshare the PCI bus

with the CPU. This is imperative, especially in cases

involving large data transfers, because the CPU gets

locked out for too long.

In block transfer mode, the DMA controller executes all of

its transfers consecutively without releasing the PCI bus.

In demand transfer mode, DMA transfer cycles continue to

occur as long as DRQ is high or terminal count is not

reached. In this mode, the DMA controller continues to

execute transfer cycles until the I/O device drops DRQ to

indicate its inability to continue providing data. For this

case, the PCI bus is held by the CS5530 until a break in

the transfers occurs.

In cascade mode, the channel is connected to another

DMA controller or to an ISA bus master, rather than to an

I/O device. In the CS5530, one of the 8237 controllers is

designated as the master and the other as the slave. The

HOLD output of the slave is tied to the DRQ0 input of the

master (Channel 4), and the master’s DACK0# output is

tied to the slave’s HLDA input.

In each of these modes, the DMA controller can be pro-

grammed for read, write, or verify transfers.

Both DMA controllers are reset at Power On Reset (POR)

to fixed priority. Since master Channel 0 is actually con-

nected to the slave DMA controller, the slave’s four DMA

channels have the highest priority, with Channel 0 as

highest and Channel 3 as the lowest. Immediately follow-

ing slave Channel 3, master Channel 1 (Channel 5) is the

next highest, followed by Channels 6 and 7.

DMA Controller Registers

The DMA controller can be programmed with standard I/O

cycles to the standard register space for DMA. The I/O

addresses of all registers for the DMA controller are listed

in Table 4-25 "DMA Channel Control Registers" on page

208.

Addresses under Master are for the 16-bit DMA channels,

and Slave corresponds to the 8-bit channels. When writ-

ing to a channel's address or word-count register, the data

is written into both the base register and the current regis-

ter simultaneously. When reading a channel address or

word count register, only the current address or word

count can be read. The base address and base word

count are not accessible for reading.

DMA Transfer Types

Each of the seven DMA channels may be programmed to

perform one of three types of transfers: read, write, or ver-

ify. Thetransfertype selecteddefines themethodusedto

transfer a BYTE or WORD during one DMA bus cycle.

For read transfer types, the CS5530 reads data from

memory andwritesittothe I/Odeviceassociatedwiththe

DMA channel.

For write transfer types, the CS5530 reads data from the

I/O device associated with the DMA channel and writes to

the memory.

The verify transfer type causes the CS5530 to execute

DMA transfer bus cycles, including generation of memory

addresses, but neither the Read nor Write command lines

are activated. This transfer type was used by DMA Chan-

nel 0 to implement DRAM refresh in the original IBM

PC/XT™.

DMA Priority

The DMA controller may be programmed for two types of

priority schemes: fixed and rotate (I/O Ports 008h[4] and

0D0h[4], as shown in Table 4-25 "DMA Channel Control

Registers" on page 208.

In fixed priority, the channels are fixed in priority order

based on the descending values of their numbers. Thus,

Channel 0 has the highest priority. In rotate priority, the

last channel to get service becomes the lowest-priority

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