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CS5530 数据表(PDF) 72 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 72 Page - National Semiconductor (TI) |
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72 / 241 page  www.national.com 72 Revision 4.1 Functional Description (Continued) 3.4.3.3 ACPI Timer Register The ACPI Timer Register (F1BAR+Memory Offset 1Ch or at I/O Port 121Ch in Silicon Revision 1.3 and above pro- vides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI is generated when bit 23 tog- gles. Table 3-28 shows the ACPI Timer Count register and the ACPI Timer SMI enable bit. V-ACPI I/O Register Space The register space designated as V-ACPI (Virtualized ACPI) I/O does not physically exist in the CS5530. ACPI is supported in the CS5530 by virtualizing this register space. In order for ACPI to be supported, the V-ACPI module must be included in the BIOS. The register descriptions that follow, are supplied here for reference only. Fixed Feature space registers are required to be imple- mented by all ACPI-compatible hardware. The Fixed Fea- ture registers in the V-ACPI solution are mapped to normal I/O space starting at offset AC00h. However, the designer can relocate this register space at compile time, hereafter referred to as ACPI_BASE. Registers within the V-ACPI I/O space must only be accessed on their defined boundaries. For example, BYTE aligned registers must not be accessed via WORD I/O instructions, WORD aligned registers must not be accessed as DWORD I/O instructions, etc. Table 3-29 summarizes the registers available in the V- ACPI I/O Register Space. The “Reference” column gives a table and page number where the bit formats for the regis- ters are located. Table 3-28. ACPI Timer Related Registers/Bits Bit Description F1BAR+Memory Offset 1Ch-1Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 31:24 Reserved: Always returns 0. 23:0 Counter Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. F0 Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 5 ACPI Timer SMI: Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Revision 1.3 and above): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. Table 3-29. V-ACPI I/O Register Space Summary ACPI_ BASE Type Align Length Name Reset Value Reference (Table 4- 32) 00h-03h R/W 4 4 P_CNT: Processor Control Register 00h Page 217 04h RO 1 1 P_LVL2: Enter C2 Power State Register 00h Page 217 05h -- 1 1 Reserved 00h Page 217 06h R/W 1 1 SMI_CMD: OS/BIOS Requests Register (ACPI enable/disable port) 00h Page 217 07h -- 1 1 Reserved 00h Page 218 08h-09h R/W 2 2 PM1A_STS: PM1A Status Register 00h Page 218 0Ah-0Bh R/W 2 2 PM1A_EN: PM1A Enable Register 00h Page 218 0Ch-0Dh R/W 4 2 PM1A_CNT: PM1A Control Register 00h Page 218 0Eh-0Fh R/W 2 2 SETUP_IDX: Setup Index Register (V-ACPI internal index register) 00h Page 219 10h-11h R/W 2 2 GPE0_STS: General Purpose Event 0 Status Register 00h Page 219 12h-13h R/W 2 2 GPE0_EN: General Purpose Event 0 Enable Register 00h Page 220 14h-17h R/W 4 4 SETUP_DATA: Setup Data Register (V-ACPI internal data register) 00h Page 220 18h-1Fh -- 8 Reserved -- For Future V-ACPI Implementations 00h Page 220 |
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