CS5530 datasheet(91/241 Pages) NSC

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Functional Description (Continued)

3.5.3

ROM Interface

The CS5530 positively decodes memory addresses

000F0000h-000FFFFFh

(64

KB)

and

FFFC0000h-

FFFFFFFFh (256 KB) at reset. These memory cycles

cause the CS5530 to claim the cycle, and generate an

ISA bus memory cycle with KBROMCS# asserted. The

CS5530 can also be configured to respond to memory

addresses

FF000000h-FFFFFFFFh

(16

MB)

and

000E0000h-000FFFFFh (128 KB).

Flash ROM is supported in the CS5530 by enabling the

KBROMCS# signal on write accesses to the ROM region.

Normally only read cycles are passed to the ISA bus, and

the KBROMCS# signal is suppressed. When the ROM

Write Enable bit (F0 Index 52h[1]) is set, a write access to

the ROM address region causes an 8-bit write cycle to

occur with MEMW# and KBROMCS# asserted.

Table 3-38 shows the ROM interface related programming

bits.

3.5.4

Megacells

The CS5530 core logic integrates:

• Two 8237-equivalent DMA controllers (DMAC) with full

32-bit addressing for DMA transfers.

• Two 8259-equivalent interrupt controllers providing 13

individually programmable external interrupts.

• An 8254-equivalent timer for refresh, timer, and

speaker logic.

• NMI control and generation for PCI system errors and

all parity errors.

• Support for standard AT keyboard controllers, reset

control, and VSA technology audio.

Table 3-38. ROM Interface Related Bits

Bit

Description

F0 Index 52h

ROM/AT Logic Control Register (R/W)

Reset Value = F8h

Upper ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = FFFC0000h-FFFFFFFFh (256 KB, Default); 1 = FF000000h-FFFFFFFFh (16 MB)

Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]).

ROM Write Enable: Assert KBROMCS# during writes to configured ROM space (configured in bits 2 and 0),

allowing Flash programming: 0 = Disable; 1 = Enable.

Lower ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = 000F0000h-000FFFFFh (64 KB, Default); 1 = 000E0000h-000FFFFFh (128 KB).

Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]).

F0 Index 5Bh

Decode Control Register 2 (R/W)

Reset Value = 20h

BIOS ROM Positive Decode: Selects PCI positive or subtractive decoding for accesses to the configured ROM space: 0

= Subtractive; 1 = Positive.

ROM configuration is at F0 Index 52h[2:0].

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