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CS5530 数据表(PDF) 38 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 38 Page - National Semiconductor (TI) |
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38 / 241 page  www.national.com 38 Revision 4.1 Signal Definitions (Continued) VID_CLK A6 I Video Clock This is the clock for the video port. This clock is completely asynchronous to the input pixel clock rate. VID_VAL B7 I Video Valid This signal indicates that valid video data is being presented on the VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance. VID_RDY B10 O Video Ready This signal indicates that the CS5530 is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance. 2.2.11 Display Interface (Continued) Signal Name Pin No. Type Description 2.2.12 DCLK PLL Signal Name Pin No. Type Description PLLLP N23 I Analog Loop Filter Capacitor Connection The loop filter requires an external capacitor (optionally a series resistor may be added) for adjustment of the loop filter response. The PLLLP pin connects this capacitor to the on-chip loop filter. PLLRO M26 I Analog VCO Center Frequency Set Resistor Connection The center frequency of the VCO is set with an external resistor con- nected between the PLLRO and PLLAGS pins. This resistor sets a con- stant current that controls the center frequency of the VCO. PLLAGS N24 I Analog Analog Sense Pin for Connection of External Components This pin is used as the return connection for all external components. This includes the ground connection for the loop filter capacitor and the PLLRO resistor. PLLVAA M25 I Analog Analog PLL Power (VDD) PLLVAA is the analog positive rail power connection to the PLL. PLLAGD N25 I Analog Analog PLL Ground (VSS) PLLAGD is the analog ground rail connection to the PLL. PLLDVD M23 I Analog Digital PLL Power (VDD) This pin is the digital VDD power connection for the PLL. PLLDGN N26 I Analog Digital PLL Ground This pin is the digital ground (VSS) connection for the PLL. |
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