CS5530 datasheet(69/241 Pages) NSC

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Functional Description (Continued)

Although not considered as device idle timers, two addi-

tional timers are provided by the CS5530. The Video Idle

Timer used for Suspend-determination and the VGA

Timer used for SoftVGA.

These timers and their associated programming bits are

listed in Tables 3-25 and 3-26.

Table 3-25. Video Idle Timer and Trap Related Registers

Bit

Description

F0 Index 81h

Power Management Enable Register 2 (R/W)

Reset Value = 00h

Video Access Idle Timer Enable: Turn on Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when

the timer expires: 0 = Disable; 1 = Enable.

If an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Register) the timer is

reloaded with the programmed count.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

F0 Index 82h

Power Management Enable Register 3 (R/W)

Reset Value = 00h

Video Access Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL Reg-

ister) an SMI is generated.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[7].

F0 Index A6h-A7h

Video Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Video Idle Timer Count: This idle timer determines when the graphics subsystem has been idle as part of the

Suspend-determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which

the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics

controller space. The counter uses a 1 second timebase.

In a GXLV processor based system the graphics controller is embedded in the CPU, so video activity is communicated to

the CS5530 via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530 also detects accesses to

standard VGA space on PCI (3Bxh, 3h, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used.

To enable this timer set F0 Index 81h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

Table 3-26. VGA Timer Related Registers

Bit

Description

Index 83h

Power Management Enable Register 4 (R/W)

Reset Value = 00h

VGA Timer Enable: Turn on VGA Timer and generate an SMI when the timer reaches 0: 0 = Disable; 1 = Enable

If an access occurs in the programmed address range the timer is reloaded with the programmed count. VGA Timer pro-

gramming is at F0 Index 8Eh and F0 Index 8Bh[6]

SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only).

Index 8Bh

General Purpose Timer 2 Control Register (R/W)

Reset Value = 00h

VGA Timer Base: Selects timebase for VGA Timer Register (F0 Index 8Eh): 0 = 1 ms; 1 = 32 µs.

Index 8Eh

VGA Timer Count Register (R/W)

Reset Value = 00h

7:0

VGA Timer Load Value: This field represents the load value for VGA Timer. It is loaded into the counter when the timer

is enabled (F0 Index 83h[3] = 1). The counter is decremented with each clock of the configured timebase (F0 Index

8Bh[6]). Upon expiration of the counter, an SMI is generated and the status is reported in F1BAR+Memory Offset

00h/02h[6] (only). Once expired, this counter must be re-initialized by either disabling and enabling it, or writing a new

count value here.

This counter’s timebase is 1 ms.

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