CS5530 datasheet(7/241 Pages) NSC

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Architecture Overview (Continued)

1.2

ISA BUS INTERFACE

The CS5530 provides an ISA bus interface for unclaimed

memory and I/O cycles on PCI. The CS5530 is the default

subtractive decoding agent and forwards all unclaimed

memory and I/O cycles to the ISA interface; however, the

CS5530 may be configured to ignore either I/O, memory

or all unclaimed cycles (subtractive decode disabled).

The CS5530 supports two modes on the ISA interface.

The default mode, Limited ISA Mode, supports the full

memory and I/O address range without ISA mastering.

The address and data buses are multiplexed together,

requiring an external latch to latch the lower 16 bits of

address of the ISA cycle. The signal SA_LATCH is gener-

ated when the data on the SA/SD bus is a valid address.

Additionally, the upper four address bits, SA[23:20] are

multiplexed on GPIO[7:4].

The second mode, ISA Master Mode, supports ISA bus

masters and requires no external circuitry. When the

CS5530 is placed in ISA Master Mode, a large number of

pins are redefined. In this mode of operation the CS5530

cannot support TFT flat panels or TV controllers, since

most of the signals used to support these functions have

been redefined. This mode is required if ISA slots or ISA

masters are used. ISA master cycles are only passed to

the PCI bus if they access memory. I/O accesses are left

to complete on the ISA bus.

For further information regarding mode selection and

operational details refer to Section 3.5.2.2 “Limited ISA

and ISA Master Modes” on page 87.

1.3

AT COMPATIBILITY LOGIC

The CS5530 integrates:

• Two 8237-equivalent DMA controllers with full 32-bit

addressing

• Two 8259-equivalent interrupt controllers providing 13

individually programmable external interrupts

• An 8254-equivalent timer for refresh, timer, and

speaker logic

• NMI control and generation for PCI system errors and

all parity errors

• Support for standard AT keyboard controllers

• Positive decode for the AT I/O register space

• Reset control

1.3.1

DMA Controller

The CS5530 supports the industry standard DMA archi-

tecture using two 8237-compatible DMA controllers in

cascaded configuration. CS5530-supported DMA func-

tions include:

• Standard seven-channel DMA support

• 32-bit address range support via high page registers

• IOCHRDY extended cycles for compatible timing

transfers

• ISA bus master device support using cascade mode

1.3.2

Programmable Interval Timer

The CS5530 contains an 8254-equivalent programmable

interval timer. This device has three timers, each with an

input frequency of 1.193 MHz.

1.3.3

Programmable Interrupt Controller

The CS5530 contains two 8259-equivalent programmable

interrupt controllers, with eight interrupt request lines

each, for a total of 16 interrupts. The two controllers are

cascaded internally, and two of the interrupt request

inputs are connected to the internal circuitry. This allows a

total of 13 externally available interrupt requests.

Each CS5530 IRQ signal can be individually selected as

edge- or level-sensitive. The PCI interrupt signals are

routed internally to the PIC IRQs.

1.4

IDE CONTROLLERS

The CS5530 integrates two PCI bus mastering, ATA-4

compatible IDE controllers. These controllers support

Ultra DMA/33(enabledinMicrosoft Windows 95 and Win-

dows NT by using a driver provided by National Semicon-

ductor), Multiword DMA and Programmed I/O (PIO)

modes. Two devices are supported on each controller.

The data-transfer speed for each device on each control-

ler can be independently programmed. This allows high-

speed IDE peripherals to coexist on the same channel as

lower speed devices. Faster devices must be ATA-4 com-

patible.

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