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Signal Definitions (Continued)

LOCK#

C22

I/O

t/s

5VT

PCI Lock

LOCK# indicates an atomic operation that may require multiple transac-

tions to complete.

If the CS5530 is currently the target of a LOCKed transaction, any other

PCI master request with the CS5530 as the target is forced to retry the

transfer.

The CS5530 does not generate LOCKed transactions.

DEVSEL#

A23

I/O

t/s

5VT

PCI Device Select

DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and sub-

tractive decoder that it is the target of the current transaction.

As an input, DEVSEL# indicates a PCI slave has responded to the current

address.

As an output, DEVSEL# is asserted one cycle after the assertion of

FRAME# and remains asserted to the end of a transaction as the result of

a positive decode. DEVSEL# is asserted four cycles after the assertion of

FRAME# if DEVSEL# has not been asserted by another PCI device when

the CS5530 is programmed to be the subtractive decode agent. The sub-

tractive decode sample point is configured in F0 Index 41h[2:1]. Subtrac-

tive decode cycles are passed to the ISA bus.

PAR

A21

I/O

t/s

5VT

PCI Parity

PAR is the parity signal driven to maintain even parity across AD[31:0]

and C/BE[3:0]#.

The CS5530 drives PAR one clock after the address phase and one clock

after each completed data phase of write transactions as a PCI master. It

also drives PAR one clock after each completed data phase of read trans-

actions as a PCI slave.

PERR#

B22

I/O

t/s

5VT

PCI Parity Error

PERR# is pulsed by a PCI device to indicate that a parity error was

detected. If a parity error was detected, PERR# is asserted by a PCI slave

during a write data phase and by a PCI master during a read data phase.

When the CS5530 is a PCI master, PERR# is an output during read trans-

fers and an input during write transfers. When the CS5530 is a PCI slave,

PERR# is an input during read transfers and an output during write trans-

fers.

Parity detection is enabled through F0 Index 04h[6]. An NMI is generated

if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index 41h[5] is

set.

SERR#

A22

I/O

5VT

PCI System Error

SERR# is pulsed by a PCI device to indicate an address parity error, data

parity error on a special cycle command, or other fatal system errors.

SERR# is an open-drain output reporting an error condition, and an input

indicating that the CS5530 should generate an NMI. As an input, SERR#

is asserted for a single clock by the slave reporting the error.

System error detection is enabled with F0 Index 04h[8]. An NMI is gener-

ated if I/O Port 061h[2] is set. PERR# can assert SERR# if F0 Index

41h[5] is set.

2.2.4

PCI Interface (Continued)

Signal Name

No.

Type

Description

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