| 数据搜索系统,热门电子元器件搜索 |
|
CS5530 数据表(PDF) 99 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5530 数据表(HTML) 99 Page - National Semiconductor (TI) |
|
99 / 241 page ![]() Revision 4.1 99 www.national.com Functional Description (Continued) Table 3-46. Interrupt Edge/Level Select Registers Bit Description I/O Port 4D0h Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h 7 IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ6 Edge or Level Select: Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 IRQ5 Edge or Level Select: Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 4 IRQ4 Edge or Level Select: Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ3 Edge or Level Select: Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 Reserved: Set to 0. 1 IRQ1 Edge or Level Select: Selects PIC IRQ1 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h 7 IRQ15 Edge or Level Select: Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ14 Edge or Level Select: Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 Reserved: Set to 0. 4 IRQ12 Edge or Level Select: Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 IRQ10 Edge or Level Select: Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 1 IRQ9 Edge or Level Select: Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |