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CS5530 数据表(PDF) 122 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 122 Page - National Semiconductor (TI) |
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122 / 241 page  www.national.com 122 Revision 4.1 Functional Description (Continued) Table 3-66. Second Level SMI Status Reporting Registers Bit Description F3BAR+Memory Offset 10h-11h Second Level Audio SMI Status Mirror Register (RC) Reset Value = 0000h 15:8 Reserved: Set to 0. 7 Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 5? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). 6 Audio Bus Master 4 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 4? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR+Memory Offset 40h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 41h[0] = 1). 5 Audio Bus Master 3 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 3? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 4 Audio Bus Master 2 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 2? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1). 3 Audio Bus Master 1 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 1? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1). 2 Audio Bus Master 0 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 0? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1). 1 Codec Serial or GPIO Interrupt SMI Status (Read to Clear): SMI was caused by a serial or GPIO interrupt from codec? 0= No; 1 = Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1. SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1. 0 I/O Trap SMI Status (Read to Clear): SMI was caused by an I/O trap? 0 = No; 1 = Yes. This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register clears the status bits. Note that bit 0 has another level (third) of SMI status reporting. A read-only “Mirror” version of this register exists at F3BAR+Memory Offset 00h. If the value of the register must be read with- out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. |
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