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CS5530 数据表(PDF) 125 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 125 Page - National Semiconductor (TI) |
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125 / 241 page  Revision 4.1 125 www.national.com Functional Description (Continued) Table 3-68. Sound Card I/O Trap and Fast Path Enable Registers Bit Description F3BAR+Memory Offset 18h-19h I/O Trap SMI Enable Register (R/W) Reset Value = 0000h 15:12 Reserved: Set to 0. 11 Fast Path Write Enable: Fast Path Write (an SMI is not generated on certain writes to specified addresses): 0 = Disable; 1 = Enable. In Fast Path Write, the CS5530 responds to writes to the following addresses: 388h, 38Ah and 38B; 2x0h, 2x2h, and 2x8h. 10:9 Fast Read: These two bits hold part of the response that the CS5530 returns for reads to several I/O locations. 8 High DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 7 Low DMA I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[12]. 6 High MPU I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 330h and 331h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 5 Low MPU I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 300h and 301h, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[11]. 4 Fast Path Read Enable/SMI Disable: Read Fast Path (an SMI is not generated on reads from specified addresses): 0 = Disable; 1 = Enable. In Fast Path Read the CS5530 responds to reads of the following addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h. Note that if neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible. 3 FM I/O Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs at I/O Port 388h to 38Bh, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. 2 Sound Card I/O Trap: 0 = Disable; 1 = Enable If this bit is enabled and an access occurs in the address ranges selected in by bits [1:0], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1]. Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR+Memory Offset 14h[10]. 1:0 Sound Card Address Range Select: These bits select the address range for the sound card I/O trap. 00 = I/O Port 220h-22Fh 10 = I/O Port 260h-26Fh 01 = I/O Port 240h-24Fh 11 = I/O Port 280h-28Fh |
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