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Revision 4.1

Functional Description (Continued)

3.8

DISPLAY SUBSYSTEM EXTENSIONS

The CS5530 incorporates extensions to the GXLV proces-

sor’s display subsystem. These include:

• Video Accelerator

- Buffers and formats input YUV video data from

GXLV processor

- Supports 8-bit interface to GXLV processor

- X & Y scaler with bilinear filter

- Color space converter (YUV to RGB)

• Video Overlay Logic

-Color key

- Data switch for graphics and video data

• Gamma RAM

- Brightness and contrast control

• Display Interface

- Integrated RGB video DACs

- VESA DDC2B/DPMS support

- Flat Panel interface

Figure 3-23 shows the data path of the display subsystem

extensions.

3.8.1

Video Interface Configuration Registers

Registers for configuring the video interface are accessed

through F4 Index 10h, the Base Address Register

(F4BAR) in Function 4. F4BAR sets the base address for

the Video Interface Configuration Registers as shown in

Table 3-70.

Note:

All Video Interface Configuration Registers have a

32-bit access granularity (only).

The following subsections describe the video interface

and the registers used for programming purposes. How-

ever, for complete bit information refer to Section 4.3.5

“Video Controller Registers - Function 4” on page 199.

Figure 3-23. 8-Bit Display Subsystem Extensions

Table 3-70. Base Address Register (F4BAR) for Video Controller Support Registers

Bit

Description

F4 Index 10h-13h

Base Address Register — F4BAR (R/W)

Reset Value = 00000000h

This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indi-

cating a 4 KB memory address range. Refer to Table 4-22 for the video controller register bit formats and reset values.

31:12

Video Controller and Clock Control Base I/O Address

11:0

Address Range (Read Only)

VID_DATA[7:0]

Input

Buffer 0

(3x360x32 bit)

Buffer 1

Buffer 2

Formatter

Scaler

Vertical

Filter

Horizontal

Filter

Color

Space

Converter

Formatter

Color Key

Color

Compare

PIXEL[23:0]

Bypass

Gamma

RAM

Video

Dither

8each

DAC

RGB to CRT

FP_DATA

Enable Gamma

Correction Register

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