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CS5530 数据表(PDF) 130 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5530
功能描述  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5530 数据表(HTML) 130 Page - National Semiconductor (TI)

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130
Revision 4.1
Functional Description (Continued)
3.8.2.3
Video Format
The video input data can be in interleaved YUV 4:2:2 or
RGB 5:6:5 format. The sequence of the individual YUV
components is selectable to one of four formats via bits
[3:2] in the Video Configuration Register (F4BAR+Mem-
ory Offset 00h[3:2]). The decode for these bits is shown in
Table 3-71.
Table 3-71. Video Input Format Bits
Bit
Description
F4BAR+Memory Offset 00h-03h
Video Configuration Register (R/W)
Reset Value = 00000000h
31
Reserved: Set to 0
30
High Speed Timing for Video Interface: High speed timings for the video interface: 0 = Disable; 1= Enable.
If bit 30 is enabled, bit 25 should be set to 0.
29
16-bit Video Interface: Allow video interface to be 16 bits: 0 = Disable; 1= Enable.
If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits.
Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29).
28
YUV 4:2:2 or 4:2:0 Mode: 0 = 4:2:2 Mode; 1= 4:2:0 Mode.
If 4:2:0 mode is selected, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode.
Note: The GXLV processor does not support 4:2:0 mode.
27
Video Line Size (DWORDs): This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description.
26
Reserved: Set to 0
25
Early Video Ready: Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video
port operation: 0 = Disable; 1 = Enable.
Bit 25 should be set to 0 if bit 30 is enabled.
24
Initial Buffer Read Address: This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description.
23:16
Initial Buffer Read Address: This field is used to preload the starting read address for the line buffers at the beginning of
each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents
the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0.
15:8
Video Line Size (DWORDs): This field represents the horizontal size of the source video data in DWORDs.
7
YFilter Enable: Vertical filter: 0 = Disable; 1= Enable.
6
XFilter Enable: Horizontal filter: 0 = Disable; 1 = Enable.
5
CSC Bypass: Allow color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather
than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC.
4
GV Select: Selects whether graphics or video data will be passed through the scaler hardware:
0 = Video data; 1 = Graphics data.
3:2
Video Input Format: This field defines the byte ordering of the video data on the VID_DATA bus.
8-Bit Mode (Value Byte Order [0:3])
16-Bit Mode (Value Byte Order [0:3])
00 = U Y0 V Y1 (also used for RGB 5:6:5 input)
00 = U Y0 V Y1 (also used for RGB 5:6:5 input)
01 = Y1 V Y0 U or 4:2:0
01 = Y0 U Y1 V
10 = Y0 U Y1 V
10 = Y1 V Y0 U or 4:2:0
11 = Y0 V Y1 U
11 = Reserved
If bit 28 is enabled, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode.
Note: U= Cb, V = Cr
1
Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of
vertical sync: 0 = Disable; 1 = Enable.
0
Video Enable: Video acceleration hardware: 0 = Disable; 1 = Enable.



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