CS5530 datasheet(133/241 Pages) NSC

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Functional Description (Continued)

3.8.4

Gamma RAM

Either the graphics or video stream may be routed

through an on-chip gamma RAM (3x256x8-bit) which can

be used for gamma-correction of either data stream, or

contrast/brightness adjustments in the case of video data.

A bypass path is provided for either the graphics or video

stream (depending on which is sent through the gamma

RAM). The two streams are merged based on the results

of the color key compare.

Configuration for this feature and the display interface are

through the Video Configuration Register (F4BAR+Mem-

ory Offset 04h). Table 3-75 shows the bit formats for this

Table 3-75. Display Configuration Register

Bit

Description

F4BAR+Memory Offset 04h-07h

Display Configuration Register (R/W)

Reset Value = 00h

DDC Input Data (Read Only): This is the DDC input data bit for reads.

Red Comparator (Read Only): This is the value of the red video DAC comparator.

Green Comparator (Read Only): This is the value of the green video DAC comparator.

Blue Comparator (Read Only): This is the value of the blue video DAC comparator.

Flat Panel On (Read Only): This bit indicates whether the attached flat panel display is powered on or off. The bit transi-

tions at the end of the power-up or power-down sequence. 0 = Off; 1 = On.

DAC External Voltage Reference Enable: This bit enables the use of an external voltage reference for the video DAC.

When enabled, an external voltage reference should be connected to the EXTVREFIN pin. When disabled, the DAC inter-

nal voltage reference will be used. 0 = Disable; 1 = Enable.

16-Bit Graphics Enable: This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset

00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit.

DDC Output Enable: This bit enables the DDC_SDA line to be driven for write data.

0 = DDC_SDA pin is input; 1 = DDC_SDA pin is output.

DDC Output Data: This is the DDC data bit.

DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit.

Palette Bypass: Selects whether graphics or video data should bypass the Gamma RAM:

0 = Video data; 1 = Graphics data.

Video/Graphics Color Key Select: Selects whether the video or graphics data stream will be used for color/chroma key-

ing. 0 = Graphics data is compared to color key; 1 = Video data is compared to color key.

19:17

Power Sequence Delay: This field selects the number of frame periods that will transpire between successive transitions

of the power sequence control lines. Valid values are 001h to 111h.

16:14

CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are

sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward

relative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline.

Flat Panel Dither Enable: This bit will enable the flat panel dithering. It enables 24 bpp display data to be approximated

with an 18-bit flat panel display. 0 = Disable; 1 = Enable.

XGA Flat Panel: This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus

into even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel.

Flat Panel Vertical Synchronization Polarity: Selects the flat panel vertical sync polarity:

0 = FP vertical sync is normally low, transitioning high during sync interval.

1 = FP vertical sync is normally high, transitioning low during sync interval.

Flat Panel Horizontal Synchronization Polarity: Selects the flat panel horizontal sync polarity:

0 = FP horizontal sync is normally low, transitioning high during sync interval.

1 = FP horizontal sync is normally high, transitioning low during sync interval.

CRT Vertical Synchronization Polarity: Selects the CRT vertical sync polarity:

0 = CRT vertical sync is normally low, transitioning high during sync interval.

1 = CRT vertical sync is normally high, transitioning low during sync interval.

CRT Horizontal Synchronization Polarity: Selects the CRT horizontal sync polarity:

0 = CRT horizontal sync is normally low, transitioning high during sync interval.

1 = CRT horizontal sync is normally high, transitioning low during sync interval.

Flat Panel Data Enable: Enables the flat panel data bus:

0 = FP_DATA [17:0] is forced low;

1 = FP_DATA [17:0] is driven based upon power sequence control.

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