CS5530 datasheet(137/241 Pages) NSC

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The Geode CS5530 is a multi-function device. Its register

space can be broadly divided into four categories in which

specific types of registers are located:

Chipset Register Space (F0-F4)

USB Controller Register Space (PCIUSB)

ISA Legacy I/O Register Space (I/O Port)

V-ACPI I/O Register Space (I/O Port)

The Chipset and the USB Controller Register Spaces are

accessed through the PCI interface using the PCI Type

One Configuration Mechanism.

The Chipset Register Space of the CS5530 is comprised

of five separate functions (F0-F4). Each with its own regis-

ter space consisting of PCI header registers and memory

or I/O mapped registers.

F0: Bridge Configuration Registers

F1: SMI Status and ACPI Timer Registers

F2: IDE Controller Registers

F3: XpressAUDIO Subsystem Registers

F4: Video Controller Registers

The PCI header is a 256-byte region used for configuring

a PCI device or function. The first 64 bytes are the same

for all PCI devices and are predefined by the PCI specifi-

cation. These registers are used to configure the PCI for

the device. The rest of the 256-byte region is used to con-

figure the device or function itself.

The USB Controller Register Space consists of the

standard PCI header registers. The USB controller sup-

ports two ports and is OpenHCI- compliant.

The ISA Legacy I/O Register Space contains all the leg-

acy compatibility I/O ports that are internal, trapped, shad-

owed, or snooped.

The V-ACPI I/O Register Space contains two types of

registers: Fixed Feature and General Purpose. These reg-

isters are emulated by the SMI handling code rather than

existing in physical hardware. To the ACPI-compliant

operating system, the SMI-base virtualization is transpar-

ent. An ACPI compliant system is one whose underlying

BIOS, device drivers, chipset and peripherals conform to

revision 1.0 or newer of the Advanced Control and Power

Interface specification.

The CS5530 V-ACPI (Virtual ACPI) solution provides the

following support:

• CPU States — C1, C2

• Sleep States — S1, S2, S4, S4BIOS, S5

• Embedded Controller (Optional) — SCI and SWI event

inputs

• General Purpose Events — Fully programmable GPE0

Event Block registers

The remaining subsections of this chapter is as follows:

• A brief discussion on how to access the registers

located in the PCI Configuration Space

• Register summary

• Detailed bit formats of all registers

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