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CS5530 数据表(PDF) 141 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 141 Page - National Semiconductor (TI) |
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141 / 241 page  Revision 4.1 141 www.national.com Register Descriptions (Continued) F7h 8 RO/RC Second Level Power Management Status Register 4 00h Page 178 F8h-FFh -- -- Reserved -- Page 178 Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary (Continued) F0 Index Width (Bits) Type Name Reset Value Reference (Table 4-14) Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary F1 Index Width (Bits) Type Name Reset Value Reference (Table 4-15) 00h-01h 16 RO Vendor Identification Register 1078h Page 179 02h-03h 16 RO Device Identification Register 0101h Page 179 04h-05h 16 R/W PCI Command Register 0000h Page 179 06h-07h 16 RO PCI Status Register 0280h Page 179 08h 8 RO Device Revision ID Register 00h Page 179 09h-0Bh 24 RO PCI Class Code Register 068000h Page 179 0Ch 8 RO PCI Cache Line Size Register 00h Page 179 0Dh 8 RO PCI Latency Timer Register 00h Page 179 0Eh 8 RO PCI Header Type Register 00h Page 179 0Fh 8 RO PCI BIST Register 00h Page 179 10h-13h 32 R/W Base Address Register (F1BAR): Sets base address for memory mapped SMI status and ACPI timer support regis- ters (summarized in Table 4-4). 00000000h Page 179 14h-FFh -- -- Reserved -- Page 179 Table 4-4. F1BAR: SMI Status and ACPI Timer Registers Summary F1BAR+ Memory Offset Width (Bits) Type Name Reset Value Reference (Table 4-16) 00h-01h 16 RO Top SMI Status Mirror Register 0000h Page 180 02h-03h 16 RC Top SMI Status Register 0000h Page 181 04h-05h 16 RO Second Level General Traps & Timers Status Mirror 0000h Page 182 06h-07h 16 RC Second Level General Traps & Timers Status Register 0000h Page 183 08h-09h 16 Read to Enable SMI Speedup Disable Register 0000h Page 183 0Ah-1Bh -- -- Reserved -- Page 183 1Ch-1Fh 32 RO ACPI Timer Count Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. 00FFFFFCh Page 183 20h-4Fh -- -- Not Used -- Page 183 50h-FFh Note: The registers located at F1BAR+Memory Offset 50h-FFh can also be accessed at F0 Index 50h-FFh. The pre- ferred method is to program these registers through the F0 Register Space. Refer to Table 4-2 "Function 0: PCI Header and Bridge Configuration Registers Summary" on page 139 for summary information. |
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