CS5530 datasheet(138/241 Pages) NSC

138 / 241 page

www.national.com

138

Revision 4.1

4.1

PCI CONFIGURATION SPACE AND ACCESS METHODS

Configuration cycles are generated in the processor. All

configuration registers in the CS5530 are accessed

through the PCI interface using the PCI Type One Config-

uration Mechanism. This mechanism uses two DWORD

I/O locations at 0CF8h and 0CFCh. The first location

(0CF8h) references the Configuration Address Register.

The second location (0CFCh) references the Configura-

tion Data Register.

To access PCI configuration space, write the Configura-

tion Address (0CF8h) Register with data that specifies the

CS5530 as the device on PCI being accessed, along with

the configuration register offset. On the following cycle, a

read or write to the Configuration Data Register (CDR)

causes a PCI configuration cycle to the CS5530. BYTE,

WORD, or DWORD accesses are allowed to the CDR at

0CFCh, 0CFDh, 0CFEh, or 0CFFh.

The CS5530 has six configuration register sets, one for

each function (F0-F4) and USB (PCIUSB). Base Address

Registers (BARs) in the PCI header registers are pointers

for additional I/O or memory mapped configuration regis-

ters.

Table 4-1 shows the PCI Configuration Address Register

(0CF8h) and how to access the PCI header registers.

Table 4-1. PCI Configuration Address Register (0CF8h)

Configuration

Space Mapping

RSVD

Bus Number

Device Number

Function

Index

DWORD

1 (Enable)

000 0000

0000 0000

xxxx x (Note)

xxx

xxxx xx

00 (Always)

Function 0 (F0): Bridge Configuration Register Space

80h

0000 0000

1001 0 or 1000 0

000

Index

Function 1 (F1): SMI Status and ACPI Timer Register Space

80h

0000 0000

1001 0 or 1000 0

001

Index

Function 2 (F2): IDE Controller Register Space

80h

0000 0000

1001 0 or 1000 0

010

Index

Function 3 (F3): XpressAUDIO Subsystem Register Space

80h

0000 0000

1001 0 or 1000 0

011

Index

Function 4 (F4): Video Controller Register Space

80h

0000 0000

1001 0 or 1000 0

100

Index

PCIUSB: USB Controller Register Space

80h

0000 0000

1001 1 or 1000 1

000

Index

Note: The device number depends upon the strapping of pin H26 (HOLD_REQ#) during POR.

Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29 (USB Register Space)

Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27 (USB Register Space)

The strapping of pin H26 can be read back in F0 Index 44h[6].

CS5530 数据表(PDF) 138 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 138 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5530 数据表(PDF) 138 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 138 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载