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Functional Description (Continued)

3.9

UNIVERSAL SERIAL BUS SUPPORT

The CS5530 integrates a Universal Serial Bus (USB) con-

troller which supports two ports. The USB controller is

OpenHCI compliant, a standard developed by Compaq,

Microsoft, and National Semiconductor.

The USB core consists of three main interface blocks: the

USB PCI interface controller, the USB host controller, and

the USB interface controller. Legacy keyboard and mouse

controllers are also supported for DOS compatibility with

those USB devices.

This document must be used along with the following pub-

lic domain reference documents for a complete functional

description of the USB controller:

• USB Specification Revision 1.0

• OpenHCI Specification, Revision 1.0

• PCI Specification, Version 2.1

3.9.1

USB PCI Controller

The PCI controller interfaces the host controller to the PCI

bus. As a master, the PCI controller is responsible for run-

ning cycles on the PCI bus on behalf of the host controller.

As a target, the PCI controller monitors the cycles on the

PCI bus and determines when to respond to these cycles.

The USB core is a PCI target when it decodes cycles to its

internal PCI configuration registers or to its internal PCI

memory mapped I/O registers.

The USB core is implemented as a unique PCI device in

the CS5530. It has its own PCI Header and Configuration

space and is mapped through PCI Configuration Mecha-

nism #1 as: Bus #0, Device #0 (AD28 = 1 or AD26 = 1),

Function #0 (referred to as PCIUSB). The USB core can

be enabled/disabled through F0 Index 43h[0].

All registers can be accessed via 8-, 16-, or 32-bit cycles

(i.e., each byte is individually selected by the byte

enables.) Registers marked as reserved, and reserved

bits within a register are not implemented and should

return 0s when read. Writes have no effect for reserved

registers. These registers are summarized in Table 3-76.

For complete bit information, see Section 4.4 “USB Con-

troller Registers - PCIUSB” on page 206.

Table 3-76. USB PCI Header Registers

PCIUSB

Name

Access

00h-01h

Vendor ID

02h-03h

Device ID

04h-05h

Command

R/W

06h-07h

Status

R/W

08h

Revision ID

09h-0Bh

Class Code

0Ch

Cache Line Size Register

R/W

0Dh

Latency Timer Register

R/W

0Eh

Header Type

0Fh

BIST Register

10h-13h

Base Address Register 0

R/W

14h-3Bh

Reserved

3Ch

Interrupt Line

R/W

3Dh

Interrupt Pin

R/W

3Eh

Minimum Grant

R/W

3Fh

Maximum Latency

R/W

40h-43h

Test Mode Enable

R/W

44h

Operational Mode Enable

R/W

45h-FFh

Reserved

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