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Revision 4.1

Functional Description (Continued)

3.9.2

USB Host Controller

In the USB core is the operational control block. It is

responsible for the host controllers operational states

(Suspend, Disable, Enable), special USB signals (Reset,

Resume), status, interrupt control, and host controller

configuration.

The host controller interface registers are PCI memory

mapped I/O. They are summarized in Table 3-77.

3.9.3

USB Power Management

At this time, USB supports minimal system level power

management features. The only power management fea-

ture implemented is the disabling of the USB clock gener-

ator

USB

Suspend

state.

Additional

power

management features will require slight modifications.

The design supports PCICLK frequencies from 0 to 33

MHz. Synchronization between the PCI and USB clock

domains is frequency independent.

Remote wakeup of USB is asynchronously implemented

from the USB Ports to PCI INTA#.

The design needs USBCLK to be operational at all times.

If it is necessary to stop the 48 MHz clock, the system

design requires that the signal used to enable/disable the

USB clock generators is also used to wake the 48 MHz

clock source. Currently, the RemoteWakeupConnected

and RemoteWakeupEnable bits in the HcControl register

are not implemented.

Table 3-77. USB Host Controller Registers

Offset

Name

00h-03h

HcRevision

04h-07h

HcControl

08h-0Bh

HcCommandStatus

0Ch-0Fh

HcInterruptStatus

10h-13h

HcInterruptEnable

14h-17h

HcInterruptDisable

18h-1Bh

HcHCCA

1Ch-1Fh

HcPeriodCurrentED

20h-23h

HcControlHeadED

24h-27h

HcControlCurrentED

28h-2Bh

HcBulkHeadED

2Ch-2Fh

HcBulkCurrentED

30h-33h

HcDoneHead

34h-37h

HcFmInterval

38h-3Bh

HcFrameRemaining

3Ch-3Fh

HcFmNumber

40h-43h

HcPeriodicStart

44h-47h

HcLSThreshold

48h-4Bh

HcRhDescriptorA

4Ch-4Fh

HcRhDescriptorB

50h-53h

HcRhStatus

54h-57h

HcRhPortStatus[1]

58h-5Ch

HcRhPortStatus[2]

100h-103h

HceControl

104h-107h

HceInput

108h-10Bh

HceOutput

10C-10Fh

HceStatus

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