CS5530 datasheet(118/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

The bus master transfers data to/from memory

responding to bus master requests from the AC97

interface. At the completion of each PRD, the bus

master’s next response depends on the settings of

the flags in the PRD.

Example - At the completion of PRD_1 an SMI is

generated because the EOP bit is set while the bus

master continues on to PRD_2. The address in the

PRD Table Address Register is incremented by 08h

and is now pointing to PRD_3. The SMI Status

Since Audio Buffer_1 is now empty, the software can

refill it.

At thecompletionof PRD_2anSMI is generated

because the EOP bit is set. The bus master then

continues ontoPRD_3. Theaddress in the PRD

Table Address Register is incremented by 08h. The

DMA SMI Status Register is read to clear the End of

Page status flag. Since Audio Buffer_2 is now empty,

the software can refill it. Audio Buffer_1 has been

refilled from the previous SMI.

PRD_3 has the JMP bit set. This means the bus

master

uses

the

address

stored

PRD_3

(Address_3) to locate the next PRD. It does not use

the address in the PRD Table Address Register to

get the next PRD. Since Address_3 is the location of

PRD_1, the bus master has looped the PRD table.

Stopping the bus master can be accomplished by not

reading the SMI Status Register End of Page status

flag. This will lead to a second EOP which causes a

Bus Master Error and pauses the bus master. In

effect, once a bus master has been enabled it never

has to be disabled, just paused. The bus master

cannot be disabled unless the bus master has been

paused or has reached an EOT.

3.7.1.5

AC97 Codec Interface

The CS5530 provides an AC97 Specification Revision

1.3, 2.0, and 2.1 compatible interface. Any AC97 codec

which supports sample rate conversion (SRC) can be

used with the CS5530. This type of codec allows for a

design which meets the requirements for PC97 and

PC98-compliant audio as defined by Microsoft Corpora-

tion.

The AC97 codec (e.g., LM4548) is the master of the serial

interface and generates the clocks to CS5530, Figure 3-

21 shows the codec and CS5530 signal connections. For

specifications on the serial interface, refer to the appropri-

ate codec manufacturer’s data sheet.

For PC speaker synthesis, the CS5530 outputs the PC

speaker signal on the PC_BEEP pin which is connected

to the PC_BEEP input of the AC97 codec.

Figure 3-21. AC97 Signal Connections

Codec Configuration/Control Registers

The codec related registers consist of four 32-bit regis-

ters:

• Codec GPIO Status Register

• Codec GPIO Control Register

• Codec Status Register

• Codec Command Register

Codec GPIO Status and Control Registers (F3BAR+

Memory Offset 00h and 04h)

The Codec GPIO Status and Control Registers are used

for codec GPIO related tasks such as enabling a codec

GPIO interrupt to cause an SMI.

Codec Status Register (F3BAR+Memory Offset 08h)

The Codec Status Register stores the codec status word.

It updates every valid Status Word slot.

Codec Control Register (F3BAR+Memory Offset 0Ch)

The Codec Control Register writes the control word to the

codec. By writing the appropriate control words to this

port, the features of the codec can be controlled. The con-

tents of this register are written to the codec during the

Control Word slot.

BITCLK

PC_BEEP

SDAT_I

SDAT_O

PC_BEEP

SDATA_IN

SDATA_OUT

AC97

BIT_CLK

24.576MHz

SYNC

External Source

Codec

Geode™

CS5530 I/O

Companion

CS5530 数据表(PDF) 118 Page - National Semiconductor (TI)

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