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CS5530 数据表(PDF) 114 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 114 Page - National Semiconductor (TI) |
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114 / 241 page  www.national.com 114 Revision 4.1 Functional Description (Continued) The six bus masters that directly drive specific slots on the AC97 interface: • Audio Bus Master 0 - Output to codec - PCI read -32-Bit - Left and right channels -Slots 3 and 4 • Audio Bus Master 1 - Input from codec -PCI write -32-Bit - Left and right channels -Slots 3 and 4 • Audio Bus Master 2 - Output to codec - PCI read -16-Bit -Slot 5 • Audio Bus Master 3 - Input from codec -PCI write -16-Bit -Slot 5 •Audio Bus Master 4 - Output to codec -PCI read - 16-Bit - Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot) •Audio Bus Master 5 - Input from codec - PCI write - 16-Bit - Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot) Bus Master Audio Configuration Registers The format for the bus master audio configuration regis- ters is similar in that each bus master has a Command Register, an SMI Status Register and a PRD Table Address Register. Programming of the bus masters is generic in many ways, although specific programming is required of bit 3 in the Command Register. This bit selects read or write control and is dependent upon which Audio Bus Master is being programmed. Table 3-62. Generic Bit Formats for Audio Bus Master Configuration Registers Bit Description Command Register (R/W) 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write Control: Set the transfer direction of Audio Bus Master X: 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. The setting of this bit is dependent upon the assigned bus master. Note: Must be R/W as a byte. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control: Controls the state of the Audio Bus Master X: 0 = Disable; 1 = Enable. Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must either be paused or have reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset. Note: Must be read and written as a BYTE. SMI Status Register (RC) 7:2 Reserved (Read to Clear) 1 Bus Master Error (Read to Clear): Hardware encountered a second EOP (end of page) before software has cleared the first?0= No; 1 = Yes. If hardware encounters a second EOP before software has cleared the first, it causes the bus master to pause until this register is read to clear the error. Note: Must be R/W as a byte. 0 End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)? 0= No; 1 = Yes. Note: Must be read and written as a BYTE. PRD Table Address (R/W) 31:2 Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master X. When written, this register points to the first entry in a PRD table. Once Audio Bus Master X is enabled (Command Reg- ister bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. |
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