CS5530 datasheet(112/241 Pages) NSC

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Functional Description (Continued)

Table 3-60. MDMA/UDMA Control Registers

Bit

Description

F2BAR+I/O Offset 24h-27h

Channel 0 Drive 0 DMA Control Register (R/W)

Reset Value = 00077771h

If bit 20 = 0, Multiword DMA

Settings for:

Multiword DMA Mode 0 = 00077771h

Multiword DMA Mode 1 = 00012121h

Multiword DMA Mode 2 = 00002020h

PIO Mode Format: 0 = Format 0; 1 = Format 1

30:21

Reserved: Set to 0.

DMA Select: DMA operation: 0 = Multiword DMA; 1 = Ultra DMA/33.

19:16

tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle)

15:12

tDR: IDE_IOR# pulse width (value + 1 cycle)

11:8

tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle)

7:4

tDW: IDE_IOW# pulse width (value + 1 cycle)

3:0

tM: IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1#

If bit 20= 1, UltraDMA/33

Settings for:

Ultra DMA/33 Mode 0 = 00921250h

Ultra DMA/33 Mode 1 = 00911140h

Ultra DMA/33 Mode 2 = 00911030h

PIO Mode Format: 0 = Format 0; 1 = Format 1

30:21

Reserved: Set to 0.

DMA Select: DMA operation: 0 = Multiword DMA, 1 = Ultra DMA/33.

19:16

tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS)

15:12

tSS: UDMA out (value + 1 cycle)

11:8

tCYC: Data setup and cycle time UDMA out (value + 2 cycles)

7:4

tRP: Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.

3:0

tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle)

F2BAR+I/O Offset 2Ch-2Fh

Channel 0 Drive 1 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 0 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

F2BAR+I/O Offset 34h-37h

Channel 1 Drive 0 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 1 Drive 0 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

F2BAR+I/O Offset 3Ch-3Fh

Channel 1 Drive 1 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

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