 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS5530 数据表(PDF) 109 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5530 数据表(HTML) 109 Page - National Semiconductor (TI) |
|
|
109 / 241 page  Revision 4.1 109 www.national.com Functional Description (Continued) Table 3-57. IDE Bus Master Command and Status Registers Bit Description F2BAR+I/O Offset 00h IDE Bus Master 0 Command Register — Primary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write Control: Sets the direction of bus master transfers: 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control: Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 to 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. F2BAR+I/O Offset 02h IDE Bus Master 0 Status Register — Primary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode) 6 Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. 1 Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. 0 Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes. F2BAR+I/O Offset 08h IDE Bus Master 1 Command Register — Secondary (R/W) Reset Value = 00h 7:4 Reserved: Set to 0. Must return 0 on reads. 3 Read or Write Control: Sets the direction of bus master transfers: 0 = PCI reads performed; 1 = PCI writes performed. This bit should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. 0 Bus Master Control: Controls the state of the bus master: 0 = Disable master; 1 = Enable master. Bus master operations can be halted by setting bit 0 = 0. Once an operation has been halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis- carded. This bit should be reset after completion of data transfer. F2BAR+I/O Offset 0Ah Bus Master 1 Status Register — Secondary (R/W) Reset Value = 00h 7 Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes; 1 = No (simplex mode) 6 Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 5 Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable. 4:3 Reserved: Set to 0. Must return 0 on reads. 2 Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes. Write 1 to clear. 1 Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes. Write 1 to clear. 0 Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
