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PC87373 数据表(PDF) 25 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 25 Page - National Semiconductor (TI) |
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25 / 174 page  1.0 Signal/Pin Connection and Description (Continued) 25 www.national.com Revision 1.1 1.4.14 Power and Ground 1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 3 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional for those signals indicated as “Programmable”. See Section 13.3 on page 157 for the values of each resistor type. XOR_OUT 30 O O4/8 VDD3 XOR Tree Output. All the device pins (except power type and analog type pins) are internally connected in a XOR tree structure. 1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recom- mended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 K Ω. If, how- ever, a TTL transceiver device is used, the value of the external pull-down resistor must be 470 Ω, and since the Serial Port pins are not able to drive this load, the external pull-down resistor must be disconnected tEPLV after VDD3 power-up (see “VDD Power-Up Reset” on page 160). Signal Pin(s) I/O Buffer Type Power Well Description VSS 8, 29, 46, 58, 78, 96, 110 I GND Ground. Ground connection for both core logic and I/O buffers, for the Main and Standby power supplies. VDD3 6, 31, 49, 60 I PWR Main 3.3V Power Supply. Powers the I/O buffers of the legacy peripherals and the LPC interface. VSB3 76, 93, 107 I PWR Standby 3.3V Power Supply. Powers the I/O buffers of the GPIO ports, SWC, Glue Functions and the on-chip Core power converter. VCORF 97 I/O PWR On-chip Core Power Converter Filter. On-chip Core power converter output. Powers the core logic of all the device modules. An external 1 µF ceramic filter capacitor must be connected between this pin and VSS. VBAT 98 I INULR Battery Power Supply. When VSB3 is off, this supply provides battery back-up to some of the SWC registers. When the functions powered by VBAT are not used, the VBAT pin must be connected to VSS through an external 10 KΩ pull-down resistor. The pin is connected to the internal logic through a series resistor for UL-compliant protection. Table 3. Internal Pull-Up and Pull-Down Resistors Signal Pin(s) Power Well Type Comments LPC Interface LPCPD 52 VDD3 PU30 Parallel Port ACK 36 VDD3 PU220 AFD_DSTRB 50 VDD3 PU440 BUSY_WAIT 35 VDD3 PD120 ERR 45 VDD3 PU220 INIT 48 VDD3 PU440 PE 34 VDD3 PU220/ PD120 Programmable Signal Pin(s) I/O Buffer Type Power Well Description |
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