PC87373 datasheet(61/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.13.3 KBC Configuration Register

This register is reset to 40h.

Power Well: VDD3 and VSB3 (see Note 1)

Location:

Index F0h

Type:

R/W

Usage Hints:

1. To change the clock frequency of the KBC:

a. Disable the KBC logical devices.

b. Change the frequency setting.

c. Enable the KBC logical devices.

2. Before swapping between the Keyboard and Mouse Interface pins, disable the KBC logical devices and their pins. After

swapping, the software must issue a synchronization command to the Keyboard and Mouse through the KBC to regain

synchronization with these devices.

Bit

76543210

Name

KBC Clock Source

Reserved

SWAP1

1. This bit is powered from the VSB3 well and is reset by VSB3 Power-Up reset.

Reserved

TRI-STATE

Control

Reset

01000000

Required

Bit

Description

7-6

KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).

Bits

7 6

Source

0 0:

8 MHz

0 1:

12 MHz (default)

1 0:

16 MHz

1 1:

Reserved

5-4

Reserved.

SWAP (Swap Keyboard and Mouse Inputs). When this bit is set, the keyboard signals (KBCLK and KBDAT) are

swapped with the mouse signals (MCLK and MDAT). This bit is used both by the KBC module and by the Key-

board/Mouse Wake-Up Detector in the SWC module. This bit is reset to the default value by VSB3 Power-Up reset

only.

0: No swapping (default)

1: Swaps the keyboard and mouse signals

2-1

Reserved.

TRI-STATE Control. When this bit is set, the Keyboard pins (KBCLK, KBDAT) and the Mouse pins (MCLK, MDAT)

are in TRI-STATE (see Section 3.3.2 on page 41), if both the Keyboard and the Mouse logical devices are inactive.

0: Normal outputs (default)

1: TRI-STATE outputs when the Keyboard and the Mouse logical devices are inactive

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