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PC87373 数据表(PDF) 36 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 36 Page - National Semiconductor (TI) |
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36 / 174 page  3.0 Device Architecture and Configuration (Continued) 36 www.national.com Revision 1.1 Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non-existing register) are ignored. Read accesses return 00h on all addresses, except for 74h and 75h (DMA configuration registers), which returns 04h (indicating no DMA channel). The configuration registers are accessible immediately after reset. 3.2.3 Standard Configuration Register Definitions In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true: • All registers are read/write. • All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write. • Write-only registers must not use read-modify-write during updates. Table 9. Standard General Configuration Registers Index Register Name Description 07h Logical Device Number This register selects the current logical device. See Table 8 for valid numbers. All other values are reserved. 20h-2Fh PC87373 Configuration PC87373 configuration registers and ID registers. Table 10. Logical Device Activate Register Index Register Name Description 30h Activate Bits 7-1: Reserved Bit 0: Logical device activation control (see Section 3.3 on page 40) 0: Disabled 1: Enabled Table 11. I/O Space Configuration Registers Index Register Name Description 60h I/O Port Base Address Bits 15 −8 Descriptor 0 Indicates selected I/O lower limit address bits 15 −8 for I/O Descriptor 0. 61h I/O Port Base Address Bits 7 −0 Descriptor 0 Indicates selected I/O lower limit address bits 7 −0 for I/O Descriptor 0. 62h I/O Port Base Address Bits 15 −8 Descriptor 1 Indicates selected I/O lower limit address bits 15 −8 for I/O Descriptor 1. 63h I/O Port Base Address Bits 7 −0 Descriptor 1 Indicates selected I/O lower limit address bits 7 −0 for I/O Descriptor 1. |
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