PC87373 datasheet(47/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.7.6

SuperI/O Configuration 6 Register (SIOCF6)

This register provides a fast way to disable one or more modules without having to access the Activate register of each (see

Section 3.3.1 on page 40).

Power Well: VDD3

Location:

Index 26h

Type:

Varies per bit

Bit

43210

Name

LOCKFDS

General-Purpose

Scratch

Reserved

SER1DIS

SER2DIS

PARPDIS

FDCDIS

Reset

00000

Bit

Type

Description

R/W1S LOCKFDS (Lock Fast Disable Configuration). When set to 1, this bit locks itself, SER1DIS,

SER2DIS, PARPDIS and FDCDIS bits in this register and GLOBEN bit in SIOCF1 register by disabling

writing to all of these bits. Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware

reset).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-5

R/W

General-Purpose Scratch.

−

Reserved.

R/W or

SER1DIS (Serial Port 1 Disable). When set to 1, this bit forces the Serial Port 1 module to be disabled

(and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

SER2DIS (Serial Port 2 Disable). When set to 1, this bit forces the Serial Port 2 module to be disabled

(and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

PARPDIS (Parallel Port Disable). When set to 1, this bit forces the Parallel Port module to be disabled

(and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

FDCDIS (Floppy Disk Controller Disable). When set to 1, this bit forces the Floppy Disk Controller

module to be disabled (and its resources released) regardless of the actual setting of its Activation bit

(index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

PC87373 数据表(PDF) 47 Page - National Semiconductor (TI)

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PC87373 数据表(PDF) 47 Page - National Semiconductor (TI)

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