PC87373 datasheet(34/174 Pages) NSC

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Device Architecture and Conﬁguration

The PC87373 device includes a collection of legacy and proprietary functional blocks. Each functional block is described in

a separate chapter. This chapter describes the structure of the PC87373 device and provides all logical device specific in-

formation, including specific implementation of generic blocks, system interface and device configuration.

3.1 OVERVIEW

The PC87373 consists of the following: up to 11 logical devices, the host interface, the Glue Functions and a central set of

configuration registers. All of these components are built around a central internal bus. The internal bus is similar to an 8-bit

ISA bus protocol. See the Block Diagram on page 1, which illustrates the blocks and the internal bus.

The host, via the LPC Bus interface, can access the modules connected to the internal bus. This interface supports 8-bit I/O

Read/Write and 8-bit DMA transactions of the LPC bus (see Section 4.2 on page 72).

The central configuration register set is ACPI compliant and supports PnP configuration. The configuration registers are struc-

tured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Re-

vision 1.0a by Intel® and Microsoft®. All system resources assigned to the functional blocks (I/O address space, IRQ numbers

and DMA channels) are configured in and managed by the central configuration register set. In addition, some function-specific

parameters are configurable through the configuration registers and distributed to the functional blocks through special control

signals.

3.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is based on a set of banked registers that are accessed via a pair of specialized registers.

3.2.1

The Index-Data Register Pair

Access to the PC87373 configuration registers is via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during reset according to the state of the hardware strapping option on

the BADDR pin. Table 7 shows the selected base addresses as a function of BADDR.

The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the

configuration register file and holds the index of the configuration register that is currently accessible via the Data register.

Reading the Index register returns the last value written to it (or the default of 00h after reset).

The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register

actually accesses the configuration register that is currently pointed to by the Index register.

Table 7. BADDR Strapping Options

BADDR

I/O Address

Index Register

Data Register

1 (default)

2Eh

2Fh

4Eh

4Fh

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