PC87373 datasheet(27/174 Pages) NSC

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Revision 1.1

2.0

Power, Reset and Clocks

2.1 POWER

2.1.1

Power Planes

The PC87373 device has four power planes (wells), as shown in the table below:

For correct operation, VSB3 must be applied before VDD3.

The battery backup voltage (VBAT) powers some of the SWC functions even when the VSB3 voltage is absent due to either

power failure or disconnection of the external AC input power. When the functions powered by VBAT are not used, the VBAT

pin must be connected to VSS through an external pull-down resistor.

To meet the UL standard requirements, a series resistor (RUL) is implemented.

2.1.2

Power States

The PC87373 device has four power states:

• Battery Fail - Backup power plane is powered off (V

BAT is inactive). This power state applies only to the SWC functions

• Power Fail - Main, Standby and Core power planes are powered off (V

DD3, VSB3 and VCORF are inactive).

• Power Off - Main power plane is powered off; the Standby and Core power planes are on (V

DD3 is inactive; VSB3 and

VCORF are active).

• Power On - Main, Standby and Core power planes are powered on (V

DD3, VSB3 and VCORF are active).

The following power state is illegal:

• The Main power plane is powered on and the Standby and Core power planes are off (i.e., V

DD3 is active; VSB and VCORF

are inactive). Operation is not guaranteed; however, at power-on/off, the device may temporarily enter this power state

due to the different rise/fall times of the VDD3 and VSB3 power supplies.

Table 5 summarizes the power states described above.

Table 4. Power Planes

Power Plane

Description

Power Pins

Ground Pins

Main

Powers the I/O buffers for the external signals1 of the

Legacy modules (Serial Ports, Parallel Port, FDC, KBC,

MIDI Port, Game Port), on-chip High-Frequency Clock

Generator, FSCM and the LPC interface, including the

buffered reset outputs

1. See the tables in Section 1.4 (pages 16

−25), speciﬁcally the Power Well column.

VDD3

VSS

Standby

Powers the I/O buffers for the external signals1 of the

GPIO ports, SWC, Glue Functions and the on-chip Core

power converter

VSB3

VSS

Core

Powers the internal (core) logic of all the device modules

VCORF

2. VCORF is generated from VSB3 by an on-chip power converter.

VSS

Backup

Powers some of the SWC functions

VBAT

VSS

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