PC87373 datasheet(8/174 Pages) NSC

8 / 174 page

Table of Contents (Continued)

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Revision 1.1

3.12.2

Logical Device 4 (SWC) Configuration ........................................................................ 59

3.13

KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION ..................................... 60

3.13.1

General Description ..................................................................................................... 60

3.13.2

Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 60

3.13.3

KBC Configuration Register ........................................................................................ 61

3.14

GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 62

3.14.1

General Description ..................................................................................................... 62

3.14.2

Logical Device 7 (GPIO) Configuration ....................................................................... 63

3.14.3

GPIO Pin Select Register (GPSEL) ............................................................................. 64

3.14.4

GPIO Pin Configuration Register 1 (GPCFG1) ........................................................... 64

3.14.5

GPIO Event Routing Register (GPEVR) ...................................................................... 65

3.14.6

GPIO Pin Configuration Register 2 (GPCFG2) ........................................................... 66

3.14.7

GPIO Mode Select Register (GPMODE) ..................................................................... 66

3.15

FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION ..................................... 67

3.15.1

General Description ..................................................................................................... 67

3.15.2

Logical Device 9 (FSCM) Configuration ...................................................................... 67

3.15.3

Fan Speed Control and Monitor Configuration Register 1 (FSCMCF1) ...................... 68

3.15.4

Fan Speed Control and Monitor Configuration Register 2 (FSCMCF2) ...................... 69

3.16

GAME PORT (GMP) CONFIGURATION ................................................................................. 70

3.16.1

Logical Device B (GMP) Configuration ........................................................................ 70

3.16.2

Game Port Configuration Register .............................................................................. 70

3.17

MUSICAL INSTRUMENT DIGITAL INTERFACE (MIDI) PORT CONFIGURATION ................. 71

3.17.1

Logical Device C (MIDI) Configuration ........................................................................ 71

3.17.2

MIDI Port Configuration Register ................................................................................. 71

4.0

LPC Bus Interface

4.1

OVERVIEW ............................................................................................................................... 72

4.2

LPC TRANSACTIONS ............................................................................................................... 72

4.3

LPCPD FUNCTIONALITY ......................................................................................................... 72

4.4

INTERRUPT SERIALIZER ........................................................................................................ 72

5.0

General-Purpose Input/Output (GPIO) Ports

5.1

OVERVIEW ............................................................................................................................... 73

5.2

BASIC FUNCTIONALITY ..........................................................................................................74

5.2.1

Configuration Options .................................................................................................. 74

5.2.2

Operation ..................................................................................................................... 75

5.3

EVENT HANDLING AND SYSTEM NOTIFICATION ................................................................ 75

5.3.1

Event Configuration ..................................................................................................... 75

5.3.2

System Notification ...................................................................................................... 76

5.4

GPIO PORT REGISTERS ......................................................................................................... 77

5.4.1

GPIO Pin Configuration Registers Structure ............................................................... 77

5.4.2

GPIO Port Runtime Register Map ............................................................................... 77

5.4.3

GPIO Data Out Register (GPDO) ................................................................................ 78

5.4.4

GPIO Data In Register (GPDI) .................................................................................... 78

5.4.5

GPIO Event Enable Register (GPEVEN) .................................................................... 79

PC87373 数据表(PDF) 8 Page - National Semiconductor (TI)

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